Ara es mostren els items 25-44 de 93

    • Effective instruction prefetching via fetch prestaging 

      Falcón Samper, Ayose Jesús; Ramírez Bellido, Alejandro; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2005)
      Text en actes de congrés
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      As technological process shrinks and clock rate increases, instruction caches can no longer be accessed in one cycle. Alternatives are implementing smaller caches (with higher miss rate) or large caches with a pipelined ...
    • Enabling preemptive multiprogramming on GPUs 

      Tanasic, Ivan; Gelado Fernandez, Isaac; Cabezas, Javier; Ramírez Bellido, Alejandro; Navarro, Nacho; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2014)
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      GPUs are being increasingly adopted as compute accelerators in many domains, spanning environments from mobile systems to cloud computing. These systems are usually running multiple applications, from one or several users. ...
    • Enabling SMT for real-time embedded systems 

      Cazorla Almeida, Francisco Javier; Knijnenburg, Peter M.W.; Sakellariou, Rizos; Fernandez Prieto, Enrique; Ramírez Bellido, Alejandro; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2004)
      Text en actes de congrés
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      In order to deal with real time constraints, current embedded processors are usually simple in-order processors with no speculation capabilities to ensure that execution times of applications are predictable. However, ...
    • Energy efficiency vs. performance of the numerical solution of PDEs: an application study on a low-power ARM-based cluster 

      Göddeke, Dominik; Komatitsch, D.; Geveler, Markus; Ribbrock, D.; Rajovic, Nikola; Puzovic, Nikola; Ramírez Bellido, Alejandro (2013-03-05)
      Article
      Accés restringit per política de l'editorial
      Power consumption and energy efficiency are becoming critical aspects in the design and operation of large scale HPC facilities, and it is unanimously recognised that future exascale supercomputers will be strongly constrained ...
    • Energy efficient HPC on embedded SoCs : optimization techniques for mali GPU 

      Grasso, Ivan; Radojković, Petar; Rajovic, Nikola; Gelado Fernandez, Isaac; Ramírez Bellido, Alejandro (Institute of Electrical and Electronics Engineers (IEEE), 2014)
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      Accés restringit per política de l'editorial
      A lot of effort from academia and industry has been invested in exploring the suitability of low-power embedded technologies for HPC. Although state-of-the-art embedded systems-on-chip (SoCs) inherently contain GPUs that ...
    • Enlarging instruction streams 

      Santana Jaria, Oliverio J.; Ramírez Bellido, Alejandro; Valero Cortés, Mateo (2007-10)
      Article
      Accés obert
      The stream fetch engine is a high-performance fetch architecture based on the concept of an instruction stream. We call a sequence of instructions from the target of a taken branch to the next taken branch, potentially ...
    • Evaluating execution time predictability of task-based programs on multi-core processors 

      Grass, Thomas Dieter; Rico Carro, Alejandro; Casas, Marc; Moretó Planas, Miquel; Ramírez Bellido, Alejandro (Springer, 2015)
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      Task-based programming models are becoming increasingly important, as they can reduce the synchronization costs of parallel programs on multi-cores. Instances of the same task type in task-based programs consist of the ...
    • Experiences with mobile processors for energy efficient HPC 

      Rajovic, Nikola; Rico Carro, Alejandro; Vipond, James; Gelado Fernandez, Isaac; Puzovic, Nikola; Ramírez Bellido, Alejandro (2013)
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      Accés restringit per política de l'editorial
      The performance of High Performance Computing (HPC) systems is already limited by their power consumption. The majority of top HPC systems today are built from commodity server components that were designed for maximizing ...
    • Explaining dynamic cache partitioning speed ups 

      Moretó Planas, Miquel; Cazorla, Francisco; Ramírez Bellido, Alejandro; Valero Cortés, Mateo (2007-01)
      Article
      Accés obert
      Cache partitioning has been proposed as an interesting alternative to traditional eviction policies of shared cache levels in modern CMP architectures: throughput is improved at the expense of a reasonable cost. However, ...
    • Exploiting different levels of parallelism in the biological sequence comparison problem 

      Sánchez Castaño, Friman; Ramírez Bellido, Alejandro; Valero Cortés, Mateo (2009-04-23)
      Text en actes de congrés
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      In the last years the fast growth of bioinformatics field has atracted the attention of computer scientists. At the same time, de exponential growth of databases that contains biological information (such as protein and ...
    • Fetching instruction streams 

      Ramírez Bellido, Alejandro; Santana Jaria, Oliverio J.; Larriba Pey, Josep; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2002)
      Text en actes de congrés
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      Fetch performance is a very important factor because it effectively limits the overall processor performance. However there is little performance advantage in increasing front-end performance beyond what the back-end can ...
    • HD-VideoBench: A benchmark for evaluating high definition digital video applications 

      Álvarez Mesa, Mauricio; Salamí San Juan, Esther; Ramírez Bellido, Alejandro; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2007)
      Text en actes de congrés
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      HD-VideoBench is a benchmark devoted to high definition (HD) digital video processing. It includes a set of video encoders and decoders (Codecs) for the MPEG-2, MPEG-4 and H.264 video standards. The applications were ...
    • High performance instruction fetch using software and hardware co-design 

      Ramírez Bellido, Alejandro (Universitat Politècnica de Catalunya, 2002-07-12)
      Tesi
      Accés obert
      En los últimos años, el diseño de procesadores de altas prestaciones ha progresado a lo largo de dos corrientes de investigación: incrementar la profundidad del pipeline para permitir mayores frecuencias de reloj, y ensanchar ...
    • Implicit vs. explicit resource allocation in SMT processors 

      Cazorla Almeida, Francisco Javier; Knijnenburg, Peter M.W.; Sakellariou, Rizos; Fernandez Garcia, Enrique; Ramírez Bellido, Alejandro; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2004)
      Text en actes de congrés
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      In a simultaneous multithreaded (SMT) architecture, the front end of a superscalar is adapted in order to be able to fetch from several threads while the back end is shared among the threads. In this paper, we describe ...
    • Instruction fetch architectures and code layout optimizations 

      Ramírez Bellido, Alejandro; Larriba Pey, Josep; Valero Cortés, Mateo (2001-11)
      Article
      Accés obert
      The design of higher performance processors has been following two major trends: increasing the pipeline depth to allow faster clock rates, and widening the pipeline to allow parallel execution of more instructions. Designing ...
    • Interleaving granularity on high bandwidth memory architecture for CMPs 

      Cabarcas, Felipe; Rico Carro, Alejandro; Etsion, Yoav; Ramírez Bellido, Alejandro (IEEE Computer Society Publications, 2010)
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      Memory bandwidth has always been a critical factor for the performance of many data intensive applications. The increasing processor performance, and the advert of single chip multiprocessors have increased the memory ...
    • Latency tolerant branch predictors 

      Santana Jaria, Oliverio J.; Ramírez Bellido, Alejandro; Valero Cortés, Mateo (IEEE Press, 2003)
      Text en actes de congrés
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      The access latency of branch predictors is a well known problem of fetch engine design. Prediction overriding techniques are commonly accepted to overcome this problem. However, prediction overriding requires a complex ...
    • Long DNA sequence comparison on multicore architectures 

      Sánchez Castaño, Friman; Cabarcas, Felipe; Ramírez Bellido, Alejandro; Valero Cortés, Mateo (Springer Verlag, 2010)
      Text en actes de congrés
      Accés restringit per política de l'editorial
      Biological sequence comparison is one of the most important tasks in Bioinformatics. Due to the growth of biological databases, sequence comparison is becoming an important challenge for high performance computing, especially ...
    • Mapping stream programs onto heterogeneous multiprocessor systems 

      Carpenter, Paul Matthew; Ramírez Bellido, Alejandro; Ayguadé Parra, Eduard (ACM Press, NY, 2009)
      Comunicació de congrés
      Accés restringit per política de l'editorial
      This paper presents a partitioning and allocation algorithm for an iterative stream compiler, targeting heterogeneous multiprocessors with constrained distributed memory and any communications topology. We introduce a ...
    • Marco para el desarrollo de la competencia transversal "comunicación eficaz" 

      López Álvarez, David; Ramírez Bellido, Alejandro (Universidad de Sevilla. Escuela Técnica Superior de Ingeniería Informática, 2011-07-05)
      Comunicació de congrés
      Accés obert
      Hay bastante consenso entre los profesores y los empleadores sobre la importancia que tiene para los ingenieros saberse comunicar. También hay consenso respecto a las bajas capacidades comunicativas de nuestros titulados. ...