Exploració per autor "Ramírez Bellido, Alejandro"
Ara es mostren els items 13-32 de 93
-
Better branch prediction through prophet/critic hybrids
Falcón Samper, Ayose Jesús; Stark, Jared; Ramírez Bellido, Alejandro; Lai, Konrad; Valero Cortés, Mateo (2005-01)
Article
Accés obertThe prophet/critic hybrid conditional branch predictor has two component predictors. The prophet uses a branch's history to predict its direction. We call this prediction and the ones for branches following it the branch ... -
Branch classification to control instruction fetch in simultaneous multithreaded architectures
Knijnenburg, Peter M.W.; Ramírez Bellido, Alejandro; Latorre Salinas, Fernando; Larriba Pey, Josep; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2002)
Text en actes de congrés
Accés obertIn simultaneous multithreaded architectures many separate threads are running concurrently, sharing processor resources, thereby realizing a high utilization rate of the available hardware. However, this also implies that ... -
Buffer sizing for self-timed stream programs on heterogeneous distributed memory multiprocessors
Carpenter, Paul Matthew; Ramírez Bellido, Alejandro; Ayguadé Parra, Eduard (Springer Verlag, 2010)
Text en actes de congrés
Accés restringit per política de l'editorialStream programming is a promising way to expose concurrency to the compiler. A stream program is built from kernels that communicate only via point-to-point streams. The stream compiler statically allocates these kernels ... -
CellSim: a validated modular heterogeneous multiprocessor simulator
Cabarcas Jaramillo, Felipe; Rico Carro, Alejandro; Ródenas Picó, David; Martorell Bofill, Xavier; Ramírez Bellido, Alejandro; Ayguadé Parra, Eduard (Thomson Editores Spain, 2007)
Text en actes de congrés
Accés obertAs the number of transistors on a chip continues increasing the power consumption has become the most important constraint in processors design. Therefore, to increase performance, computer architects have decided to use ... -
Code layout optimizations for transaction processing workloads
Ramírez Bellido, Alejandro; Barroso, Luiz A; Gharachorloo, Kourosh; Cohn, Robert; Larriba Pey, Josep; Lowney, P. Geoffrey; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2001)
Text en actes de congrés
Accés obertCommercial applications such as databases and Web servers constitute the most important market segment for high-performance servers. Among these applications, on-line transaction processing (OLTP) workloads provide a ... -
COMalaWEB: plataforma basada en noves tecnologies aplicades a la docència
Fernández Rubio, Juan Antonio; Fernández Prades, Carlos; Ramírez Bellido, Alejandro; Cabrera-Bean, Margarita; Pomar Berry, Christian (2005-02)
Text en actes de congrés
Accés obertLes possibilitats que ens ofereixen les noves tecnologies de la informació aplicades a l’àmbit de la docència és un tema encara no prou ben explotat. Aquest projecte pretén investigar aquests conceptes mitjançant la creació ... -
Comparing last-level cache designs for CMP architectures
Vega, Augusto; Rico Carro, Alejandro; Cabarcas, Felipe; Ramírez Bellido, Alejandro; Valero Cortés, Mateo (2010)
Text en actes de congrés
Accés restringit per política de l'editorialThe emergence of hardware accelerators, such as graphics processing units (GPUs), has challenged the interaction between processing elements (PEs) and main memory. In architectures like the Cell/B.E. or GPUs, the PEs ... -
CUsched: multiprogrammed workload scheduling on GPU architectures
Tanasic, Ivan; Gelado Fernandez, Isaac; Cabezas, Javier; Navarro, Nacho; Ramírez Bellido, Alejandro; Valero Cortés, Mateo (2013)
Report de recerca
Accés obertGraphic Processing Units (GPUs) are currently widely used in High Performance Computing (HPC) applications to speed-up the execution of massively-parallel codes. GPUs are well-suited for such HPC environments because ... -
Data placement in HPC architectures with heterogeneous off-chip memory
Pavlovic, Milan; Puzovic, Nikola; Ramírez Bellido, Alejandro (Institute of Electrical and Electronics Engineers (IEEE), 2013)
Text en actes de congrés
Accés obertThe performance of HPC applications is often bounded by the underlying memory system's performance. The trend of increasing the number of cores on a chip imposes even higher memory bandwidth and capacity requirements. The ... -
Dcache Warn: an I-fetch policy to increase SMT efficiency
Cazorla Almeida, Francisco Javier; Ramírez Bellido, Alejandro; Valero Cortés, Mateo; Fernandez Garcia, Enrique (Institute of Electrical and Electronics Engineers (IEEE), 2004)
Text en actes de congrés
Accés obertSimultaneous multithreading (SMT) processors increase performance by executing instructions from multiple threads simultaneously. These threads share the processor's resources, but also compete for them. In this environment, ... -
DIA: A complexity-effective decoding architecture
Santana Jaria, Oliverio J.; Falcón Samper, Ayose Jesus; Ramírez Bellido, Alejandro; Valero Cortés, Mateo (2009-04)
Article
Accés obertFast instruction decoding is a true challenge for the design of CISC microprocessors implementing variable-length instructions. A well-known solution to overcome this problem is caching decoded instructions in a hardware ... -
Dynamically controlled resource allocation in SMT processors
Cazorla Almeida, Francisco Javier; Ramírez Bellido, Alejandro; Valero Cortés, Mateo; Fernandez Prieto, Enrique (Institute of Electrical and Electronics Engineers (IEEE), 2004)
Text en actes de congrés
Accés obertSMT processors increase performance by executing instructions from several threads simultaneously. These threads use the resources of the processor better by sharing them but, at the same time, threads are competing for ... -
Effective instruction prefetching via fetch prestaging
Falcón Samper, Ayose Jesús; Ramírez Bellido, Alejandro; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2005)
Text en actes de congrés
Accés obertAs technological process shrinks and clock rate increases, instruction caches can no longer be accessed in one cycle. Alternatives are implementing smaller caches (with higher miss rate) or large caches with a pipelined ... -
Enabling preemptive multiprogramming on GPUs
Tanasic, Ivan; Gelado Fernandez, Isaac; Cabezas, Javier; Ramírez Bellido, Alejandro; Navarro, Nacho; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2014)
Text en actes de congrés
Accés obertGPUs are being increasingly adopted as compute accelerators in many domains, spanning environments from mobile systems to cloud computing. These systems are usually running multiple applications, from one or several users. ... -
Enabling SMT for real-time embedded systems
Cazorla Almeida, Francisco Javier; Knijnenburg, Peter M.W.; Sakellariou, Rizos; Fernandez Prieto, Enrique; Ramírez Bellido, Alejandro; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2004)
Text en actes de congrés
Accés obertIn order to deal with real time constraints, current embedded processors are usually simple in-order processors with no speculation capabilities to ensure that execution times of applications are predictable. However, ... -
Energy efficiency vs. performance of the numerical solution of PDEs: an application study on a low-power ARM-based cluster
Göddeke, Dominik; Komatitsch, D.; Geveler, Markus; Ribbrock, D.; Rajovic, Nikola; Puzovic, Nikola; Ramírez Bellido, Alejandro (2013-03-05)
Article
Accés restringit per política de l'editorialPower consumption and energy efficiency are becoming critical aspects in the design and operation of large scale HPC facilities, and it is unanimously recognised that future exascale supercomputers will be strongly constrained ... -
Energy efficient HPC on embedded SoCs : optimization techniques for mali GPU
Grasso, Ivan; Radojković, Petar; Rajovic, Nikola; Gelado Fernandez, Isaac; Ramírez Bellido, Alejandro (Institute of Electrical and Electronics Engineers (IEEE), 2014)
Text en actes de congrés
Accés restringit per política de l'editorialA lot of effort from academia and industry has been invested in exploring the suitability of low-power embedded technologies for HPC. Although state-of-the-art embedded systems-on-chip (SoCs) inherently contain GPUs that ... -
Enlarging instruction streams
Santana Jaria, Oliverio J.; Ramírez Bellido, Alejandro; Valero Cortés, Mateo (2007-10)
Article
Accés obertThe stream fetch engine is a high-performance fetch architecture based on the concept of an instruction stream. We call a sequence of instructions from the target of a taken branch to the next taken branch, potentially ... -
Evaluating execution time predictability of task-based programs on multi-core processors
Grass, Thomas Dieter; Rico Carro, Alejandro; Casas, Marc; Moretó Planas, Miquel; Ramírez Bellido, Alejandro (Springer, 2015)
Text en actes de congrés
Accés restringit per política de l'editorialTask-based programming models are becoming increasingly important, as they can reduce the synchronization costs of parallel programs on multi-cores. Instances of the same task type in task-based programs consist of the ... -
Experiences with mobile processors for energy efficient HPC
Rajovic, Nikola; Rico Carro, Alejandro; Vipond, James; Gelado Fernandez, Isaac; Puzovic, Nikola; Ramírez Bellido, Alejandro (2013)
Text en actes de congrés
Accés restringit per política de l'editorialThe performance of High Performance Computing (HPC) systems is already limited by their power consumption. The majority of top HPC systems today are built from commodity server components that were designed for maximizing ...