Exploració per autor "Canal Corretger, Ramon"
Ara es mostren els items 47-66 de 83
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Platform-agnostic steal-time measurement in a guest operating system
(2018-10)
Report de recerca
Accés obertSteal time is a key performance metric for applications executed in a virtualized environment. Steal time measures the amount of time the processor is preempted by code outside the virtualized environment. This, in turn, ... -
Power- and complexity-aware issue queue designs
(2003-09)
Article
Accés obertThe improved performance of current microprocessors brings with it increasingly complex and power-dissipating issue logic. Recent proposals introduce a range of mechanisms for tackling this problem. -
Power- and Performance - Aware Architectures
(Universitat Politècnica de Catalunya, 2004-06-14)
Tesi
Accés obertThe scaling of silicon technology has been ongoing for over forty years. We are on the way to commercializing devices having a minimum feature size of one-tenth of a micron. The push for miniaturization comes from the ... -
Power-efficient spilling techniques for chip multiprocessors
(Springer Verlag, 2010)
Text en actes de congrés
Accés restringit per política de l'editorialCurrent trends in CMPs indicate that the core count will increase in the near future. One of the main performance limiters of these forthcoming microarchitectures is the latency and high-demand of the on-chip network and ... -
Power/performance/thermal design-space exploration for multicore architectures
(2008-05)
Article
Accés obertMulticore architectures have been ruling the recent microprocessor design trend. This is due to different reasons: better performance, thread-level parallelism bounds in modern applications, ILP diminishing returns, better ... -
Predictive reliability and fault management in exascale systems: State of the art and perspectives
(2020-09)
Article
Accés obertPerformance and power constraints come together with Complementary Metal Oxide Semiconductor technology scaling in future Exascale systems. Technology scaling makes each individual transistor more prone to faults and, due ... -
Privacy preserving deep learning framework in fog computing
(Springer, 2020)
Text en actes de congrés
Accés obertNowadays, the widespread use of mobile devices has raised serious cybersecurity challenges. Mobile services and applications use deep learning (DL) models for the modelling, classification and recognition of complex data, ... -
Process variability in sub-16nm bulk CMOS technology
(2012-03-01)
Report de recerca
Accés obertThe document is part of deliverable D3.6 of the TRAMS Project (EU FP7 248789), of public nature, and shows and justifies the levels of variability used in the research project for sub-18nm bulk CMOS technologies. -
Processor Design
(Universitat Politècnica de Catalunya, 2017)
Apunts
Accés obert -
Protecting RSA hardware accelerators against differential fault analysis through residue checking
(Institute of Electrical and Electronics Engineers (IEEE), 2019)
Text en actes de congrés
Accés obertHardware accelerators for cryptographic algorithms are ubiquitously deployed in nowadays consumer and industrial products. Unfortunately, the HW implementations of such algorithms often suffer from vulnerabilities that ... -
REEM: failure/non-failure region estimation method for SRAM yield analysis
(Institute of Electrical and Electronics Engineers (IEEE), 2014)
Text en actes de congrés
Accés restringit per política de l'editorialThe big challenge that we face today for designing resilient memories is the huge number of simulations needed to arrive at a good estimate of memory's yield. A lot of work has come up recently focusing on the reduction ... -
Replacing 6T SRAMs with 3T1D DRAMs in the L1 data cache to combat process variability
(2008-02)
Article
Accés obertWith continued technology scaling, process variations will be especially detrimental to six-transistor static memory structures (6T SRAMs). A memory architecture using three-transistor, one-diode DRAM (3T1D) cells in the ... -
Review on suitable eDRAM configurations for next nano-metric electronics era
(2018-03)
Article
Accés obertWe summarize most of our studies focused on the main reliability issues that can threat the gain-cells eDRAM behavior when it is simulated at the nano-metric device range has been collected in this review. So, to outperform ... -
SafeLS: An open source implementation of a lockstep NOEL-V RISC-V core
(Institute of Electrical and Electronics Engineers (IEEE), 2023)
Text en actes de congrés
Accés obertMicrocontrollers running safety-critical applications with high integrity requirements must provide appropriate safety measures to manage random hardware faults. For instance, automotive safety regulations (e.g., ISO26262) ... -
SafeX: Open source hardware and software components for safety-critical systems
(Institute of Electrical and Electronics Engineers (IEEE), 2022)
Text en actes de congrés
Accés obertRISC-V Instruction Set Architecture (ISA) emerges as an opportunity to develop open source hardware without being subject to expensive licenses or export restrictions. A plethora of initiatives are nowadays developing ... -
Securing RSA hardware accelerators through residue checking
(2021-01)
Article
Accés obertCircuits for the hardware acceleration of cryptographic algorithms are ubiquitously deployed in consumer and industrial products. Although being secure from a mathematical point of view, such accelerators may expose several ... -
Small-layered feed-forward and convolutional neural networks for efficient P wave earthquake detection
(2022-11-15)
Article
Accés restringit per política de l'editorialThe number and efficiency of seismic networks have steadily increase over time delivering large datasets to be analyzed for earthquake occurrence. Automatic tools for accurate earthquake detection are under emerging and ... -
Software-controlled operand-gating
(IEEE Computer Society, 2004)
Text en actes de congrés
Accés obertOperand gating is a technique for improving processor energy efficiency by gating off sections of the data path that are unneeded by short-precision (narrow) operands. A method for implementing software-controlled power ... -
SRAM arrays with built-in parity computation for real-time error detection in cache tag arrays
(Institute of Electrical and Electronics Engineers (IEEE), 2021)
Text en actes de congrés
Accés obertThis work proposes an SRAM array with built-in real-time error detection (RTD) capabilities. Each cell in the new RTD-SRAM array computes its part of the real-time parity of an SRAM array column on-the-fly. RTD based arrays ... -
SSFB: a highly-efficient and scalable simulation reduction technique for SRAM yield analysis
(European Interactive Digital Advertising Alliance (EDAA), 2014)
Text en actes de congrés
Accés restringit per política de l'editorialEstimating extremely low SRAM failure-probabilities by conventional Monte Carlo (MC) approach requires hundreds-of-thousands simulations making it an impractical approach. To alleviate this problem, failure-probability ...
