Exploració per autor "Canal Corretger, Ramon"
Ara es mostren els items 33-52 de 83
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Lightning talks of EduHPC 2022
Qasem, Apan; Anzt, Hartwig; Ayguadé Parra, Eduard; Cahil, Katharine; Canal Corretger, Ramon; Chan, Jany; Fosler-Lussier, Eric; Llosa Espuny, José Francisco; Martorell Bofill, Xavier; Sancho Samsó, María Ribera (Institute of Electrical and Electronics Engineers (IEEE), 2022)
Text en actes de congrés
Accés obertThe lightning talks at EduHPC provide an opportunity to share early results and insights on parallel and distributed computing (PDC) education and training efforts. The four lightning talks at EduHPC 2022 cover a range of ... -
Lightweight protection of cryptographic hardware accelerators against differential fault analysis
Lasheras Mas, Ana; Canal Corretger, Ramon; Rodríguez Luna, Eva; Cassano, Luca (Institute of Electrical and Electronics Engineers (IEEE), 2020)
Text en actes de congrés
Accés obertHardware acceleration circuits for cryptographic algorithms are largely deployed in a wide range of products. The HW implementations of such algorithms often suffer from a number of vulnerabilities that expose systems to ... -
Malicious website detection through deep learning algorithms
Gutiérrez Escobar, Norma; Otero Calviño, Beatriz; Rodríguez Luna, Eva; Canal Corretger, Ramon (Springer Nature, 2022)
Text en actes de congrés
Accés obertTraditional methods that detect malicious websites, such as blacklists, do not update frequently, and they cannot detect new attackers. A system capable of detecting malicious activity using Deep Learning (DL) has been ... -
MASkIt: soft error rate estimation for combinatorial circuits
Anglada Sánchez, Martí; Canal Corretger, Ramon; Aragon, Juan Luis; González Colás, Antonio María (Institute of Electrical and Electronics Engineers (IEEE), 2016)
Text en actes de congrés
Accés restringit per política de l'editorialIntegrated circuits are getting increasingly vulnerable to soft errors; as a consequence, soft error rate (SER) estimation has become an important and very challenging goal. In this work, a novel approach for SER estimation ... -
MeRLiN: Exploiting dynamic instruction behavior for fast and accurate microarchitecture level reliability assessment
Kaliorakis, Manolis; Gizopoulos, Dimitris; Canal Corretger, Ramon; González Colás, Antonio María (Association for Computing Machinery (ACM), 2017)
Text en actes de congrés
Accés obertEarly reliability assessment of hardware structures using microarchitecture level simulators can effectively guide major error protection decisions in microprocessor design. Statistical fault injection on microarchitectural ... -
Mitigation strategies of the variability in 3T1D cell memories scaled beyond 22nm
Amat Bertran, Esteve; García Almudéver, Carmen; Aymerich Capdevila, Nivard; Canal Corretger, Ramon; Rubio Sola, Jose Antonio (2012)
Text en actes de congrés
Accés obert3T1D cell has been stated as a valid alternative to be implemented on L1 memory cache to substitute 6T, highly affected by device variability. In this contribution, we have shown that 22nm 3T1D memory cells present significant ... -
Modem gain-cell memories in advanced technologies
Amat Bertran, Esteve; Canal Corretger, Ramon; Rubio Sola, Jose Antonio (Institute of Electrical and Electronics Engineers (IEEE), 2018)
Text en actes de congrés
Accés obertWith the advent of the slowdown in DRAM capacitor scaling [1] and the increased reliability problems of traditional 6T SRAM memories [2], industry and academia have looked for alternative memory cells. Among those, gain- ... -
MODEST: a model for energy estimation under spatio-temporal variability
Ganapathy, Shrikanth; Canal Corretger, Ramon; González Colás, Antonio María; Rubio Sola, Jose Antonio (Institute of Electrical and Electronics Engineers (IEEE), 2010)
Text en actes de congrés
Accés restringit per política de l'editorialEstimation of static and dynamic energy of caches is critical for high-performance low-power designs. Commercial CAD tools performing energy estimation statically are not aware of the changing operating and environmental ... -
Nanoelectronic Circuit Design
Canal Corretger, Ramon (Universitat Politècnica de Catalunya, 2016)
Apunts
Accés obert -
NEUROPULS: NEUROmorphic energy-efficient secure accelerators based on Phase change materials aUgmented siLicon photonicS
Pavanello, Fabio; Marchand, Cedric; O’Connor, Ian; Orobtchouk, Regis; Mandorlo, Fabien; Letartre, Xavier; Cueff, Sebastien; Brando Guillaumes, Axel; Cazorla Almeida, Francisco Javier; Canal Corretger, Ramon (Institute of Electrical and Electronics Engineers (IEEE), 2023)
Text en actes de congrés
Accés obertThis special session paper introduces the Horizon Europe NEUROPULS project, which targets the development of secure and energy-efficient RISC-V interfaced neuromorphic accelerators using augmented silicon photonics technology. ... -
On the effectiveness of hybrid mechanisms on reduction of parametric failures in caches
Ganapathy, Shrikanth; Canal Corretger, Ramon; González Colás, Antonio María; Rubio Sola, Jose Antonio (2011-12-05)
Report de recerca
Accés restringit per política de l'editorialIn this paper, we provide an insight on the different proactive read/write assist methods (wordline boosting & adaptive body biasing) that help in preventing (and reducing) parametric failures when coupled with reactive ... -
On the photometric homogeneity of type IA supernovae
Bravo Guil, Eduardo; Domínguez, Inmaculada; Isern Vilaboy, Jordi; Canal Corretger, Ramon; Höflich, P.; Labay, Javier (1993-03)
Article
Accés obertThe dependence of the characteristics of the light curves of Type Ia supernovae on the ignition density of the progenitor white dwarf is studied with the aid of two models of propagation of the thermonuclear burning front: ... -
On the use of probabilistic worst-case execution time estimation for parallel applications in high performance systems
Fusi, Matteo; Mazzocchetti, Fabio; Farres, Albert; Kosmidis, Leonidas; Canal Corretger, Ramon; Cazorla Almeida, Francisco Javier; Abella Ferrer, Jaume (Multidisciplinary Digital Publishing Institute (MDPI), 2020-03-01)
Article
Accés obertSome high performance computing (HPC) applications exhibit increasing real-time requirements, which call for effective means to predict their high execution times distribution. This is a new challenge for HPC applications ... -
Optimization of FinFET-based gain cells for low power sub-vt embedded drams
Amat, Esteve; Calomarde Palomino, Antonio; Canal Corretger, Ramon; Rubio Sola, Jose Antonio (2018-06-01)
Article
Accés obertSub-threshold circuits (sub-V T) are a promising alternative in the implementation of low power electronics. The implementation of gain-cell embedded DRAMs (eDRAMs) based on FinFET devices requires a careful design to ... -
Platform-agnostic steal-time measurement in a guest operating system
Verdú Mulà, Javier; Costa Prats, Juan José; Otero Calviño, Beatriz; Rodríguez Luna, Eva; Pajuelo González, Manuel Alejandro; Canal Corretger, Ramon (2018-10)
Report de recerca
Accés obertSteal time is a key performance metric for applications executed in a virtualized environment. Steal time measures the amount of time the processor is preempted by code outside the virtualized environment. This, in turn, ... -
Power- and complexity-aware issue queue designs
Abella Ferrer, Jaume; Canal Corretger, Ramon; González Colás, Antonio María (2003-09)
Article
Accés obertThe improved performance of current microprocessors brings with it increasingly complex and power-dissipating issue logic. Recent proposals introduce a range of mechanisms for tackling this problem. -
Power- and Performance - Aware Architectures
Canal Corretger, Ramon (Universitat Politècnica de Catalunya, 2004-06-14)
Tesi
Accés obertThe scaling of silicon technology has been ongoing for over forty years. We are on the way to commercializing devices having a minimum feature size of one-tenth of a micron. The push for miniaturization comes from the ... -
Power-efficient spilling techniques for chip multiprocessors
Herrero Abellanas, Enric; González, José; Canal Corretger, Ramon (Springer Verlag, 2010)
Text en actes de congrés
Accés restringit per política de l'editorialCurrent trends in CMPs indicate that the core count will increase in the near future. One of the main performance limiters of these forthcoming microarchitectures is the latency and high-demand of the on-chip network and ... -
Power/performance/thermal design-space exploration for multicore architectures
Monchiero, Matteo; Canal Corretger, Ramon; González Colás, Antonio María (2008-05)
Article
Accés obertMulticore architectures have been ruling the recent microprocessor design trend. This is due to different reasons: better performance, thread-level parallelism bounds in modern applications, ILP diminishing returns, better ... -
Predictive reliability and fault management in exascale systems: State of the art and perspectives
Canal Corretger, Ramon; Hernández Luz, Carles; Tornero Gavilá, Rafael; Cilardo, Alessandro; Massari, Giuseppe; Reghenzani, Federico; Fornaciari, William; Zapater Sancho, Marina; Atienza, David; Oleksiak, Ariel; Wojciech Piatek, Poznan; Abella Ferrer, Jaume (2020-09)
Article
Accés obertPerformance and power constraints come together with Complementary Metal Oxide Semiconductor technology scaling in future Exascale systems. Technology scaling makes each individual transistor more prone to faults and, due ...