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Vista preliminarDataTítolAutor(s)
2012A novel variation-tolerant 4T-DRAM cell with enhanced soft-error toleranceGanapathy, Shrikanth; Canal Corretger, Ramon; Alexandrescu, Dan; Costenaro, Enrico; González Colás, Antonio María; Rubio Sola, Jose Antonio
2012A Novel variation-tolerant 4T-DRAM with enhance soft-error toleranceGanapathy, Shrikanth; Canal Corretger, Ramon; Alexandrescu, Dan; Costenaro, Enrico; González Colás, Antonio María; Rubio Sola, Jose Antonio
2013An energy-efficient and scalable eDRAM-based register file architecture for GPGPUJing, Naifeng; Shen, Yao; Lu, Yao; Ganapathy, Shrikanth; Mao, Zhigang; Guo, Minyi; Canal Corretger, Ramon; Liang, Xiaoyao
2009An hybrid eDRAM/SRAM macrocell to implement first-level data cachesValero, Alejandro; Sahuquillo, Julio; Petit, Salvador; Lorente, Vicente; Canal Corretger, Ramon; López, Pedro; Duato, José
2013Combining RAM technologies for hard-error recovery in L1 data caches working at very-low power modesLorente, Vicente; Valero, Alejandro; Sahuquillo, Julio; Petit, Salvador; Canal Corretger, Ramon; López, Pedro; Duato, José
des-2012Comparison of SRAM cells for 10-nm SOI FinFETs under process and environmental variationsJaksic, Zoran; Canal Corretger, Ramon
2014DRAM-based coherent caches and how to take advantage of the coherence protocol to reduce the refresh energyJaksic, Zoran; Canal Corretger, Ramon
Dynamic fine-grain body biasing ....pdf.jpg15-abr-2011Dynamic fine-grain body biasing of caches with latency and leakage 3T1D-based monitorsGanapathy, Shrikanth; Canal Corretger, Ramon; González Colás, Antonio María; Rubio Sola, Jose Antonio
2013Effectiveness of hybrid recovery techniques on parametric failuresGanapathy, Shrikanth; Canal Corretger, Ramon; González Colás, Antonio María; Rubio Sola, Jose Antonio
2010Elastic cooperative caching: an autonomus dynamically adaptive memory hierarchy for chip multiprocessorsHerrero Abellanas, Enric; González, José; Canal Corretger, Ramon
2012Enhancing 3T DRAMs for SRAM replacement under 10nm tri-gate SOI FinFETsJaksic, Zoran; Canal Corretger, Ramon
20-nov-2013Impact of finfet and III-V/Ge technology on logic and memory cell behaviorAmat, Esteve; Calomarde Palomino, Antonio; García Almudéver, Carmen; Aymerich Capdevila, Nivard; Canal Corretger, Ramon; Rubio Sola, Jose Antonio
2011Impact of positive bias temperature instability (PBTI)Aymerich Capdevila, Nivard; Ganapathy, Shrikanth; Rubio Sola, Jose Antonio; Canal Corretger, Ramon; González Colás, Antonio María
2014INFORMER: an integrated framework for early-stage memory robustness analysisGanapathy, Shrikanth; Canal Corretger, Ramon; Alexandrescu, Dan; Costenaro, Eric; González Colás, Antonio María; Rubio Sola, Jose Antonio
EAB_DCIS12.pdf.jpg2012Mitigation strategies of the variability in 3T1D cell memories scaled beyond 22nmAmat Bertran, Esteve; García Almudéver, Carmen; Aymerich, Nivard; Canal Corretger, Ramon; Rubio Sola, Jose Antonio
5-des-2011On the effectiveness of hybrid mechanisms on reduction of parametric failures in cachesGanapathy, Shrikanth; Canal Corretger, Ramon; González Colás, Antonio María; Rubio Sola, Jose Antonio
075_bravo.pdf.jpgmar-1993On the photometric homogeneity of type IA supernovaeBravo Guil, Eduardo; Domínguez, Inmaculada; Isern, Jordi; Canal Corretger, Ramon; Höflich, P.; Labay, Javier
2010Power-efficient spilling techniques for chip multiprocessorsHerrero Abellanas, Enric; González, José; Canal Corretger, Ramon
Variability_Scenarios.pdf.jpg1-mar-2012Process variability in sub-16nm bulk CMOS technologyRubio Sola, Jose Antonio; Figueras Pàmies, Joan; Vatajelu, Elena Ioana; Canal Corretger, Ramon
2014SSFB: a highly-efficient and scalable simulation reduction technique for SRAM yield analysisRana, Manish; Canal Corretger, Ramon
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