Exploració per autor "Canal Corretger, Ramon"
Ara es mostren els items 7-26 de 83
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A novel variation-tolerant 4T-DRAM cell with enhanced soft-error tolerance
(IEEE Computer Society Publications, 2012)
Text en actes de congrés
Accés restringit per política de l'editorialIn view of device scaling issues, embedded DRAM (eDRAM) technology is being considered as a strong alternative to conventional SRAM for use in on-chip memories. Memory cells designed using eDRAM technology in addition ... -
A Real-Time Error Detection (RTD) architecture and its use for reliability and post-silicon validation for F/F based memory arrays
(Institute of Electrical and Electronics Engineers (IEEE), 2022-04-01)
Article
Accés obertThis work proposes in-situ Real-Time Error Detection (RTD): embedding hardware in a memory array for detecting a fault in the array when it occurs, rather than when it is read. RTD breaks the serialization between data ... -
A survey of deep learning techniques for cybersecurity in mobile networks
(2021-06-07)
Article
Accés obertThe widespread use of mobile devices, as well as the increasing popularity of mobile services has raised serious cybersecurity challenges. In the last years, the number of cyberattacks has grown dramatically, as well as ... -
A survey of machine and deep learning methods for privacy protection in the Internet of things
(Multidisciplinary Digital Publishing Institute (MDPI), 2023-01-21)
Article
Accés obertRecent advances in hardware and information technology have accelerated the proliferation of smart and interconnected devices facilitating the rapid development of the Internet of Things (IoT). IoT applications and services ... -
An automotive case study on the limits of approximation for object detection
(2023-05)
Article
Accés restringit per política de l'editorialThe accuracy of camera-based object detection (CBOD) built upon deep learning is often evaluated against the real objects in frames only. However, such simplistic evaluation ignores the fact that many unimportant objects ... -
An energy-efficient and scalable eDRAM-based register file architecture for GPGPU
(ACM, 2013)
Text en actes de congrés
Accés restringit per política de l'editorialThe heavily-threaded data processing demands of streaming multiprocessors (SM) in a GPGPU require a large register file (RF). The fast increasing size of the RF makes the area cost and power consumption unaffordable for ... -
An hybrid eDRAM/SRAM macrocell to implement first-level data caches
(Association for Computing Machinery (ACM), 2009)
Text en actes de congrés
Accés restringit per política de l'editorialSRAM and DRAM cells have been the predominant technologies used to implement memory cells in computer systems, each one having its advantages and shortcomings. SRAM cells are faster and require no refresh since reads are ... -
Challenges in deeply heterogeneous high performance systems
(Institute of Electrical and Electronics Engineers (IEEE), 2019)
Text en actes de congrés
Accés obertRECIPE (REliable power and time-ConstraInts-aware Predictive management of heterogeneous Exascale systems) is a recently started project funded within the H2020 FETHPC programme, which is expressly targeted at exploring ... -
Circuit propagation delay estimation through multivariate regression-based modeling under spatio-temporal variability
(Institute of Electrical and Electronics Engineers (IEEE), 2010)
Text en actes de congrés
Accés restringit per política de l'editorialWith every process generation, the problem of variability in physical parameters and environmental conditions poses a great challenge to the design of fast and reliable circuits. Propagation delays which decide circuit ... -
Combining RAM technologies for hard-error recovery in L1 data caches working at very-low power modes
(2013)
Text en actes de congrés
Accés restringit per política de l'editorialLow-power modes in modern microprocessors rely on low frequencies and low voltages to reduce the energy budget. Nevertheless, manufacturing induced parameter variations can make SRAM cells unreliable producing hard errors ... -
Comparison of SRAM cells for 10-nm SOI FinFETs under process and environmental variations
(2012-12)
Article
Accés restringit per política de l'editorialWe explore the 6T and 8T SRAM design spaces through read static noise margin (RSNM), word-line write margin, and leakage for future 10-nm FinFETs. Process variations are based on the ITRS and modeled at device (TCAD) level. ... -
Cross-layer system reliability assessment framework for hardware faults
(Institute of Electrical and Electronics Engineers (IEEE), 2016)
Text en actes de congrés
Accés obertSystem reliability estimation during early design phases facilitates informed decisions for the integration of effective protection mechanisms against different classes of hardware faults. When not all system abstraction ... -
Deep-learning based detection for cyber-attacks in IoT networks: A distributed attack detection framework
(Springer Nature, 2023-02-04)
Article
Accés obertThe widespread use of smart devices and the numerous security weaknesses of networks has dramatically increased the number of cyber-attacks in the internet of things (IoT). Detecting and classifying malicious traffic is ... -
DRAM-based coherent caches and how to take advantage of the coherence protocol to reduce the refresh energy
(European Interactive Digital Advertising Alliance (EDAA), 2014)
Text en actes de congrés
Accés restringit per política de l'editorialRecent technology trends has turned DRAMs into an interesting candidate to substitute traditional SRAM-based on-chip memory structures (i.e. register file, cache memories). Nevertheless, a major problem to introduce these ... -
Dynamic cluster assignment mechanisms
(Institute of Electrical and Electronics Engineers (IEEE), 2000)
Text en actes de congrés
Accés obertClustered microarchitectures are an effective approach to reducing the penalties caused by wire delays inside a chip. Current superscalar processors have in fact a two-cluster microarchitecture with a naive code partitioning ... -
Dynamic fine-grain body biasing of caches with latency and leakage 3T1D-based monitors
(2011-04-15)
Report de recerca
Accés obertIn this paper, we propose a dynamically tunable fine-grain body biasing mechanism to reduce active & standby leakage power in caches under process variations. -
Effectiveness of hybrid recovery techniques on parametric failures
(Institute of Electrical and Electronics Engineers (IEEE), 2013)
Text en actes de congrés
Accés restringit per política de l'editorialModern day microprocessors effectively utilise supply voltage scaling for tremendous power reduction. The minimum voltage beyond which a processor cannot operate reliably is defined as V ddmin. On-chip memories like caches ... -
Elastic cooperative caching: an autonomus dynamically adaptive memory hierarchy for chip multiprocessors
(Association for Computing Machinery (ACM), 2010)
Text en actes de congrés
Accés restringit per política de l'editorialNext generation tiled microarchitectures are going to be limited by off-chip misses and by on-chip network usage. Furthermore, these platforms will run an heterogeneous mix of applications with very different memory needs, ... -
Enhancing 3T DRAMs for SRAM replacement under 10nm tri-gate SOI FinFETs
(IEEE Computer Society Publications, 2012)
Text en actes de congrés
Accés restringit per política de l'editorialIn this paper, we pr esent the dynamic 3T memory cell for future 10nm tri-gate FinFETs as a potential replacement for classical 6T SRAM cell for implementation in high speed cache memories. We investigate read access ... -
ETS 2022 ORGANIZING COMMITTEE
(2022-05)
Text en actes de congrés
Accés obert
