Exploració per autor "Moreno Aróstegui, Juan Manuel"
Ara es mostren els items 33-52 de 54
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JubiTool: Unified design flow for the perplexus SIMD hardware accelerator
(IEEE Computer Society Publications, 2009)
Text en actes de congrés
Accés obertThis paper presents a new unified design flow developed within the Perplexus project that aims to accelerate parallelizable data-intensive applications in the context of ubiquitous computing. This contribution relies ... -
Loopback strategy for in-vehicle network processing in automotive gateway network on chip
(Association for Computing Machinery (ACM), 2021)
Text en actes de congrés
Accés restringit per política de l'editorialIn this work, authors introduce an innovative loopback strategy for In-Vehicle Network (IVN) processing in automotive gateway (GW) Network on Chip. The new proposed architecture is fully HW centric, and allows performing ... -
Loopback strategy for TSN-compliant traffic queueing and shaping in automotive gateways
(Institute of Electrical and Electronics Engineers (IEEE), 2021)
Text en actes de congrés
Accés restringit per política de l'editorialIn this work, authors present a Hardware (HW)based loopback strategy which is a new paradigm in networkprocessing, for HW efficient and cost-effective integration of TimeSensitive Networking (TSN) functionalities within ... -
On the ability of adaptation of speech signals and data hiding
(2012-11-15)
Article
Accés restringit per política de l'editorialThe efficient wavelet masking is a scheme of speech-in-speech hiding based on the ability of adaptation of speech signals under the hypothesis “any (speech) secret signal may seem similar to a (speech) host signal if its ... -
Performance evaluation and scaling of a multiprocessor architecture emulating complex SNN algorithms
(Springer Verlag, 2010-09)
Article
Accés restringit per política de l'editorialThe performance analysis of an efficient multiprocessor architecture that allows accelerating the emulation of large-scale Spiking Neural Networks (SNNs) is reported. After describing the architecture and the complex SNN ... -
POETIC-CUBES
(Fundación Telefónica, 2012)
Capítol de llibre
Accés restringit per política de l'editorial -
POEtic-cubes: atención y emergencia. Hardware bioinspirado para instalaciones artísticas
(2009)
Article
Accés obertEn este artículo se explica la experiencia obtenida después de elaborar diversos trabajos artísticos en torno al tema de la atención con propuestas de hardware bioinspirado, es decir, con una solución técnica que se basa ... -
Real-time, speech-in-speech hiding scheme based on least significant bit substitution and adaptive key
(Elsevier, 2013-03-05)
Article
Accés restringit per política de l'editorialReal-time, embedded speech-in-speech hiding has not been widely researched. Nevertheless, it could be useful, among other cases, in secure mobile telephony. In this paper, we propose a new scheme of data hiding which takes ... -
REMPARK system assessment: Main results
(River Publishers, 2017-07)
Capítol de llibre
Accés obertParkinson's Disease (PD) is a neurodegenerative disorder that manifests with motor and non-motor symptoms. PD treatment is symptomatic and tries to alleviate the associated symptoms through an adjustment of the medication. ... -
REMPARK: when AI and technology meet parkinson disease assessment
(Lodz University of Technology, 2013)
Text en actes de congrés
Accés restringit per política de l'editorialREMPARK project objective is to develop a personal health system with closed loop detection, response and action capabilities for the assessment and possible management of Parkinson's Disease (PD) patients. The project is ... -
RTL implementation and analysis of fixed priority, round robin, and matrix arbiters for the NoC’s routers
(Institute of Electrical and Electronics Engineers (IEEE), 2016)
Comunicació de congrés
Accés restringit per política de l'editorialNetworks-on-Chip (NoC) is an emerging on-chip interconnection centric platform that influences modern high speed communication infrastructure to improve the performance of many-core System-on-Chip (SoCs) designs. The core ... -
RTL Implementation And Analysis of Fixed Priority,Round Robin, and Matrix Arbiters for the NoC’sRouters
(Institute of Electrical and Electronics Engineers (IEEE), 2016)
Text en actes de congrés
Accés restringit per política de l'editorialNetworks-on-Chip (NoC) is an emerging on-chip interconnection centric platform that influences modern high speed communication infrastructure to improve the performance of many-core System-on-Chip (SoCs) designs. The core ... -
Self-adaptive hardware architecture with parallel processing capabilities and dynamic reconfiguration
(Association for Computing Machinery (ACM), 2017)
Text en actes de congrés
Accés restringit per política de l'editorialThis paper describes a new self-adaptive hardware architecture with fault tolerance capabilities and a development system that allows the creation of applications. This bioinspired architecture is based on an array of ... -
Speech scrambling based on imitation of a target speech signal with non-confidential content
(2014-05-15)
Article
Accés restringit per política de l'editorialThis paper shows a new approach of speech scrambling using imitation to produce a scrambled speech signal with intelligible content. The secret message imitates a target speech signal with non-confidential content through ... -
SpiNDeK: An integrated design tool for the multiprocessor emulation of complex bioinspired spiking neural networks
(IEEE Computer Society Publications, 2009)
Text en actes de congrés
Accés restringit per política de l'editorialSpiNDeK (Spiking Neural Network Design Kit) is an integrated design tool intended to support the development of emulation of complex bioinspired neural networks. In this work, the most relevant aspects of the tool are ... -
Synchronous digital implementation of the AER communication scheme for emulating large-scale spiking neural networks models
(IEEE Computer Society Publications, 2009-08)
Text en actes de congrés
Accés obertIn this paper we shall present a fully synchronous digital implementation of the Address Event Representation (AER) communication scheme that has been used in the PERPLEXUS chip in order to permit the emulation ... -
The Equilibrium-action cycle as a mechanism for design-evolution integration in autonomous behavior design
(IEEE, 2012)
Text en actes de congrés
Accés restringit per política de l'editorial -
The future roadmap of in-vehicle network processing: a HW-centric (R-)evolution
(Institute of Electrical and Electronics Engineers (IEEE), 2022-06-27)
Article
Accés obertThe automotive industry is undergoing a deep revolution. With the race towards autonomous driving, the amount of technologies, sensors and actuators that need to be integrated in the vehicle increases exponentially. This ... -
The imbalance network and incremental evolution for mobile robot nervous system design
(2013)
Text en actes de congrés
Accés restringit per política de l'editorialAutomatic design of neurocontrollers (as in Evoluationary Robotics) utilizes incremental evolution to solve for more complex behaviors. Also manual design techniques such as task decomposition are employed. Manual design ... -
Traffic shaping engine for time sensitive networking integration within in-vehicle networks
(Institute of Electrical and Electronics Engineers (IEEE), 2021)
Text en actes de congrés
Accés restringit per política de l'editorialIn this work authors present a Traffic Shaping Engine (TSE) intended for the next generation of Time Sensitive Networking (TSN) compliant Network/System on Chip (NoC/SoC) devices, targeting especially the automotive industry. ...
