Ara es mostren els items 75-94 de 98

    • Review of energy harvesting techniques and applications for microelectronics 

      Mateu, Loreto; Moll Echeto, Francisco de Borja (International Society for Optical Engineering, 2005)
      Text en actes de congrés
      Accés obert
      The trends in technology allow the decrease in both size and power consumption of complex digital systems. This decrease in size and power gives rise to new paradigms of computing and use of electronics, with many small ...
    • Robust sequential circuits design technique for low voltage and high noise scenarios 

      García Leyva, Lancelot; Rivera Dueñas, Juan; Calomarde Palomino, Antonio; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio (2016)
      Text en actes de congrés
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      All electronic processing components in future deep nanotechnologies will exhibit high noise level and/ or low S/N ratios because of the extreme voltage reduction and the nearly erratic nature of such devices. ...
    • Sargantana: an academic SoC RISC-V processor in 22nm FDSOI technology 

      Doblas Font, Max; Candón Arenas, Gerard; Carril Gil, Xavier; Dominguez de la Rocha, Marc; Erra, Enric; González Trejo, Alberto; Jiménez, Víctor; Kostalampros, Ioannis-Vatistas; Langarita Benítez, Rubén; Leyva Santes, Neiel; López Paradís, Guillem; Mendoza Escobar, Jonnatan; Oltra Oltra, Josep Angel; Pavón Rivera, Julián; Ramírez Lazo, Cristóbal; Rodas Quiroga, Narcís; Reggiani, Enrico; Rodriguez, Mario; Rojas Morales, Carlos; Ruiz Ramirez, Abraham Josafat; Safadi Figueroa, Hugo Ernesto; Soria Pardos, Víctor; Vargas Valdivieso, Iván; Arreza, Fernando; Figueras Bagué, Roger; Fontova Muste, Pau; Marimon Illana, Joan; Aragonès Cervera, Xavier; Cristal Kestelman, Adrián; Mateo Peña, Diego; Moll Echeto, Francisco de Borja; Moretó Planas, Miquel; Palomar Pérez, Óscar; Sonmez, Nehir; Unsal, Osman Sabri; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2023)
      Comunicació de congrés
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      This paper describes the Sargantana System on chip (SoC), a 64-bit RISC-V single core processor designed by a number of academic institutions and manufactured in 22 nm FDSOI technology: BSC, UPC, UB, UAB, CIC-IPN and IMB-CNM ...
    • Semi-analytic discrete time model of a 1-stage CC-CP 

      Palma Carmona, Kenneth; Moll Echeto, Francisco de Borja (2019-11-20)
      Report de recerca
      Accés obert
      This paper employs a linear, discrete-time State- Space model of a CMOS Cross-Coupled Charge Pump (CCCP.) The discrete-time model is based on the analytic solution of the differential equations at each semi-period. This ...
    • SET and noise fault tolerant circuit design techniques: application to 7 nm FinFET 

      Calomarde Palomino, Antonio; Amat Bertran, Esteve; Moll Echeto, Francisco de Borja; Vigara Campmany, Julio Enrique; Rubio Sola, Jose Antonio (2014-04-01)
      Article
      Accés obert
      In the near future of high component density and low-power technologies, soft errors occurring not only in memory systems and latches but also in the combinational parts of logic circuits will seriously affect the reliable ...
    • Simulated leakage power analysis attack of the trivium stream cipher 

      Palma Carmona, Kenneth; Moll Echeto, Francisco de Borja (Institute of Electrical and Electronics Engineers (IEEE), 2022)
      Text en actes de congrés
      Accés restringit per política de l'editorial
      In this paper, the theoretical basis for power analysis attacks on the Trivium utilizing leakage current as a side-channel are presented. The analysis is first established in the case of an ideal implementation without the ...
    • Statistical characterization and modeling of random telegraph noise effects in 65nm SRAM cells 

      Martinez, Javier; Rodriguez, Rosa; Nafría Maqueda, Montserrat; Torrents, Gabriel; Bota, Sebastian A .; Segura, Jaume; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio (Institute of Electrical and Electronics Engineers (IEEE), 2017)
      Text en actes de congrés
      Accés restringit per política de l'editorial
      Random Telegraph Noise (RTN) effects are investigated in 65nm SRAM cells by using a new characterization method that provides a significant measurement time reduction. The variability induced in commercial SRAM cells is ...
    • System-level simulation of a self-powered sensor with piezoelectric energy harvesting 

      Mateu, Loreto; Moll Echeto, Francisco de Borja (2007-10)
      Text en actes de congrés
      Accés obert
      This paper presents a complete system simulation of a self-powered communication module. The components are described with the Verilog-A language, that allows to merge the electrical and mechanical models of the system. ...
    • Systematic and random variability analysis of two different 6T-SRAM layout topologies 

      Amat Bertran, Esteve; Amatlle, E.; Gómez González, Sergio; Aymerich Capdevila, Nivard; García Almudéver, Carmen; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio (2013-09)
      Article
      Accés obert
    • TFET-Based power management circuit for RF energy harvesting 

      Nunes Cavalheiro, David Manuel; Moll Echeto, Francisco de Borja; Valtchev, Stanimir (2016-11-14)
      Article
      Accés obert
      This paper proposes a Tunnel FET (TFET)-based power management circuit (PMC) for ultra-low power RF energy harvesting applications. In contrast with conventional thermionic devices, the band-to-band tunneling mechanism of ...
    • Transistor sizing analysis of regular fabrics 

      Marranghello, Felipe S.; Dal Bem, Vinicius; Reis, André Inácio; Ribas, Renato P.; Moll Echeto, Francisco de Borja (2011)
      Text en actes de congrés
      Accés obert
      This paper presents an extensive transistor sizing analysis for regular transistor fabrics. Several evaluation methods have been exploited, such as DC simulations, ring oscillators and single-gate open chain structures. ...
    • Tunnel FET device characteristics for RF energy harvesting passive rectifiers 

      Nunes Cavalheiro, David Manuel; Moll Echeto, Francisco de Borja (2015-06)
      Comunicació de congrés
      Accés obert
      The lack of high power conversion efficiency in RF passive rectifier circuits at sub-µW power levels with current MOSFET technologies is directly related with the difficulty of the transistors in conducting the required ...
    • Turtle Logic: A new probabilistic design methodology of nanoscale digital circuits 

      García Leyva, Lancelot; Calomarde Palomino, Antonio; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio (IEEE Press. Institute of Electrical and Electronics Engineers, 2010)
      Text en actes de congrés
      Accés obert
      As devices and operating voltages are scaled down, future circuits will be plagued by higher soft error rates, reduced noise margins and defective devices. A key challenge for the future technologies is to retain circuit ...
    • Turtle logic: Novel IC digital probabilistic design methodology 

      García Leyva, Lancelot; Rubio Sola, Jose Antonio; Moll Echeto, Francisco de Borja; Calomarde Palomino, Antonio (2010)
      Text en actes de congrés
      Accés obert
      Future electronic devices are expected to operate at lower voltage supply to save power, especially in ultimate and new technologies. The resulting reduction of logic levels approaches the thermal noise limit, and ...
    • Two examples of approximate arithmetic to reduce hardware complexity and power consumption 

      Fornt Mas, Jordi; Jin, Leixin; Etxezarreta, Imanol; Fontova, Pau; Altet Sanahujes, Josep; Calomarde Palomino, Antonio; Morancho Llena, Enrique; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio (Institute of Electrical and Electronics Engineers (IEEE), 2022)
      Comunicació de congrés
      Accés obert
      As the end of Moore's Law approaches, electronic system designers must find ways to keep up with the ever increasing computational demands of the modern era. Some computationally intensive applications, such as multimedia ...
    • Variability-tolerant memristor-based ratioed logic in crossbar array 

      Escudero López, Manuel; Rubio Sola, Jose Antonio; Moll Echeto, Francisco de Borja; Vourkas, Ioannis (Institute of Electrical and Electronics Engineers (IEEE), 2018)
      Text en actes de congrés
      Accés obert
      The advent of the first TiO2-based memristor in 2008 revived the scientific interest both from academia and industry for this de- vice technology, with several emerging applications including that of logic circuits. Several ...
    • Variation tolerant self-adaptive clock generation architecture based on a ring oscillator 

      Pérez Puigdemont, Jordi; Calomarde Palomino, Antonio; Moll Echeto, Francisco de Borja (Institute of Electrical and Electronics Engineers (IEEE), 2012)
      Comunicació de congrés
      Accés obert
      In this work we propose a self-adaptive clock based on a ring oscillator as the solution for the increasing uncertainty in the critical path delay. This increase in uncertainty forces to add more safety margins to the ...
    • Variations-aware circuit designs for microprocessors 

      Pons Solé, Marc; Moll Echeto, Francisco de Borja; Abella Ferrer, Jaume (2010)
      Comunicació de congrés
      Accés obert
      A new trend that is becoming dominant is to improve layout regularity so that the layouts to be printed are more repetitive and easy to manufacture. Our proposal is to push to the limit layout regularity to minimize ...
    • VCTA: A Via-Configurable Transistor Array regular fabric 

      Pons Solé, Marc; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio; Abella Ferrer, Jaume; Vera Rivera, Francisco Javier; González Colás, Antonio María (IEEE Computer Society Publications, 2010)
      Text en actes de congrés
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      Layout regularity is introduced progressively by integrated circuit manufacturers to reduce the increasing systematic process variations in the deep sub-micron era. In this paper we focus on a scenario where layout regularity ...
    • Via-configurable transistors array: a regular design technique to improve ICs yield 

      Pons, Marc; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio; Abella Ferrer, Jaume; Vera Rivera, Francisco Javier; González Colás, Antonio María (Institute of Electrical and Electronics Engineers (IEEE), 2007)
      Text en actes de congrés
      Accés obert
      Process variations are a major bottleneck for digital CMOS integrated circuits manufacturability and yield. That is why regular techniques with different degrees of regularity are emerging as possible solutions. Our ...