Exploració per autor "Moll Echeto, Francisco de Borja"
Ara es mostren els items 52-71 de 98
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Linear, time-invariant model of the dynamics of a CMOS CC-CP
(Institute of Electrical and Electronics Engineers (IEEE), 2019)
Comunicació de congrés
Accés obertThis paper presents the development of a linear dynamic model of a MOS Cross Coupled Charge Pump (CC-CP) suitable for low voltage energy harvesting systems in the form of a Discrete-Time State-Space set of equations ... -
Lithography aware regular cell design based on a predictive technology model
(2010-12)
Article
Accés restringit per política de l'editorialAs semiconductor technology advances into the nanoscale era, optical effects such as channel narrowing, corner rounding or line-end pullback are critical to accomplish circuit yield specifications. It is well-demonstrated ... -
Lithography aware regular cell design based on a predictive technology model
(2010)
Text en actes de congrés
Accés obertAs semiconductor technology advances into the nanoscale era, optical effects such as channel narrowing, corner rounding or line-end pullback are critical to accomplish circuit yield specifications. It is well-demonstrated ... -
Lithography parametric yield estimation model to predict layout pattern distortions with a reduced set of lithography simulations
(2014-07-01)
Article
Accés obertA lithography parametric yield estimation model is presented to evaluate the lithography distortion in a printed layout due to lithography hotspots. The aim of the proposed yield model is to provide a new metric that enables ... -
Local variations compensation with DLL-based body bias generator for UTBB FD-SOI technology
(Institute of Electrical and Electronics Engineers (IEEE), 2015)
Text en actes de congrés
Accés restringit per política de l'editorialLocal variations are increasingly important in new technologies. This paper presents the design of adaptive circuits based on the concept of Adaptive Body Bias Islands and a Forward and Reverse Body Bias Generator for FDSOI ... -
Logic synthesis for manufacturability considering regularity and lithography printability
(IEEE Computer Society Publications, 2013)
Text en actes de congrés
Accés restringit per política de l'editorialThis paper presents a novel yield model for integrated circuits manufacturing, considering lithography printability problems as a source of yield loss. The use of regular layouts can improve the printability of IC layouts, ... -
Measurements of process variability in 40-nm regular and nonregular layouts
(2014-02-01)
Article
Accés restringit per política de l'editorialAs technology scales down, IC design is becoming more difficult due to the increase in process variations, which translates into a dispersion of circuit parameter values thus degrading manufacturing yield. Regular layouts ... -
Measuring the tolerance of self-adaptive clocks to supply voltage noise
(2011)
Text en actes de congrés
Accés obertSimultaneous switching noise has become an important issue due to its signal integrity and timing implications. Therefore a lot of time and resources are spent during the PDN design to minimize the supply voltage variation. ... -
Mechanical energy harvesting taxonomy for industrial environments: application to the railway industry
(2020-07-01)
Article
Accés obertTraditional industry is experiencing a worldwide evolution with Industry 4.0. Wireless sensor networks (WSNs) have a main role in this evolution as an essential part of data acquisition. The way in which WSNs are powered ... -
Memristive logic in crossbar memory arrays: Variability-aware design for higher reliability
(2019-01-01)
Article
Accés obertThe advent of the first TiO 2 -based memristor in 2008 revived the scientific interest both from academia and industry for this device technology and has so far led to several emerging applications including logic and ... -
Monitor strategies for variability reduction considering correlation between power and timing variability
(IEEE Press. Institute of Electrical and Electronics Engineers, 2011)
Text en actes de congrés
Accés restringit per política de l'editorialAs CMOS technology scales, Process, Voltage and Temperature (PVT) variations have an increasing impact on, performance and power consumption of the electronic devices. Variability causes an undesirable dispersion of ... -
New redundant logic design concept for high noise and low voltage scenarios
(2011-12)
Article
Accés restringit per política de l'editorialThis paper presents a new redundant logia design concept named Turtle Logic(TL).It is a new probabilistic logic method based on port redundancy and complementary data, oriented toward emerging technologies beyond CMOS, ... -
Noise generation and coupling mechanisms in deep-submicron IC's
(2002-09)
Article
Accés obertOn-chip noise generation and coupling is an important issue in deep-submicron technologies. Advanced IC technology faces new challenges to ensure function and performance integrity. Selecting adequate test techniques ... -
Novel charge pump converter with Tunnel FET devices for ultra-low power energy harvesting sources
(Institute of Electrical and Electronics Engineers (IEEE), 2015)
Comunicació de congrés
Accés obertCompared to conventional technologies, the superior electrical characteristics of III-V Tunnel FET (TFET) devices can highly improve the process of energy harvesting conversion at ultra-low input voltage operation ... -
Novel redundant logic design for noisy low voltage scenarios
(2013)
Text en actes de congrés
Accés restringit per política de l'editorialThe concept worked in this paper named Turtle Logic (TL) is a probabilistic logic method based on port redundancy and complementary data, oriented to emerging CMOS technologies and beyond, where the thermal noise could be ... -
Novel UHF passive rectifier with tunnel FET devices
(Institute of Electrical and Electronics Engineers (IEEE), 2015)
Text en actes de congrés
Accés obertThe increase of the losses in UHF passive rectifiers with Tunnel FET devices at large RF AC amplitudes are mainly due to the high reverse current inherent of this technology when subjected to high reverse bias conditions. ... -
On anomaly-aware structural health monitoring at the extreme edge
(Institute of Electrical and Electronics Engineers (IEEE), 2023-01-01)
Article
Accés obertSelf-awareness has been successfully utilized to create adaptive behaviors in wireless sensor nodes. However, its adoption can be daunting in scenarios, such as structural health monitoring, where the monitored environment ... -
On evaluating temperature as observable for CMOS technology variability
(2010-05-26)
Text en actes de congrés
Accés obertThe temperature at surface of a silicon die depends on the activity of the circuits placed on it. In this paper, it is analyzed how Process, Voltage and Temperature (PVT) variations affect simultaneously some figures ... -
On the variability-aware design of memristor-based logic circuits
(Institute of Electrical and Electronics Engineers (IEEE), 2018)
Text en actes de congrés
Accés obertEver since the advent of the first TiO 2 -based memristor and the respective linear model published by Hewlett-Packard Labs, several behavioral models of memristors have been published. Such models capture the fundamental ... -
Optimum piezoelectric bending beam structures for energy harvesting using shoe inserts
(SAGE Publications Ltd, 2005-10)
Article
Accés obertThe small amount of power demanded by many present-day electronic devices opens up the possibility to convert part of the energy present in the environment into electrical energy, using several methods. One such method is ...
