E-prints UPC >

Llistant per Autor Moll Echeto, Francisco de Borja

Vista preliminar	Data	Títol	Autor(s)
	2011	Design guidelines towards compact litho-friendly regular cells	Gómez Fernández, Sergio; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio; Elhoj, Martin; Schlinker, Guilherme; Woolaway, Nigel
	2011	Design of complex circuits using the via-configurable transistor array regular layout fabric	Pons Solé, Marc; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio; Abella Ferrer, Jaume; Vera Rivera, Francisco Javier; González Colás, Antonio María
	jun-2006	Energy macro-model for on chip interconnection buses	Mendoza Vázquez, Raymundo; Pons Solé, Marc; Moll Echeto, Francisco de Borja; Figueras, Joan
	2007	Error probability in synchronous digital circuits due to power supply noise	Martorell Cid, Ferran; Pons, M; Rubio Sola, Jose Antonio; Moll Echeto, Francisco de Borja
	jul-2007	Error probability in synchronous digital circuits due to power supply noise	Martorell Cid, Ferran; Pons Solé, Marc; Rubio, Antonio; Moll Echeto, Francisco de Borja
	2011	Fast time-to-market with via-configurable transistor array regular fabric: A delay-locked loop design case study	González Colás, Antonio María; Pons Solé, Marc; Barajas Ojeda, Enrique; Mateo Peña, Diego; López González, Juan Miguel; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio; Abella Ferrer, Jaume; Vera Rivera, Francisco Javier
	9-jun-2009	FOCSI: A new layout regularity metric	Pons Solé, Marc; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio; Abella Ferrer, Jaume; Vera Rivera, Francisco Javier; González Colás, Antonio María
	des-2010	Lithography aware regular cell design based on a predictive technology model	Gómez Fernández, Sergio; Moll Echeto, Francisco de Borja
	2010	Lithography aware regular cell design based on a predictive technology model	Gómez Fernández, Sergio; Moll Echeto, Francisco de Borja
	2011	Measuring the tolerance of self-adaptive clocks to supply voltage noise	Pérez Puigdemont, Jordi; Moll Echeto, Francisco de Borja; Cortadella Fortuny, Jordi
	2011	Monitor strategies for variability reduction considering correlation between power and timing variability	Mauricio Ferré, Juan; Moll Echeto, Francisco de Borja; Altet Sanahujes, Josep
	des-2011	New redundant logic design concept for high noise and low voltage scenarios	García Leyva, Lancelot; Andrade Miceli, Dennis Michael; Gómez Fernández, Sergio; Calomarde Palomino, Antonio; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio
	set-2002	Noise generation and coupling mechanisms in deep-submicron IC's	Aragonès Cervera, Xavier; González Jiménez, José Luis; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio
	26-mai-2010	On evaluating temperature as observable for CMOS technology variability	Altet Sanahujes, Josep; Gómez Salinas, Dídac; Dufis, Cédric Yvan; González Jiménez, José Luis; Mateo Peña, Diego; Aragonès Cervera, Xavier; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio
	2005	Optimum piezoelectric bending beam structures for energy harvesting using shoe inserts	Mateu, Loreto; Moll Echeto, Francisco de Borja
	jun-2007	Power supply noise and logic error probability	Andrade Miceli, Dennis Michael; Martorell Cid, Ferran; Pons Solé, Marc; Moll Echeto, Francisco de Borja; Rubio, Antonio
	2005	Review of energy harvesting techniques and applications for microelectronics	Mateu, Loreto; Moll Echeto, Francisco de Borja
	2007	System-level simulation of a self-powered sensor with piezoelectric energy harvesting	Mateu, Loreto; Moll Echeto, Francisco de Borja
	2011	Transistor sizing analysis of regular fabrics	Marranghello, Felipe S.; Dal Bem, Vinicius; Reis, André I.; Ribas, Renato P.; Moll Echeto, Francisco de Borja
	2010	Turtle Logic: A new probabilistic design methodology of nanoscale digital circuits	García Leyva, Lancelot; Calomarde Palomino, Antonio; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio