Exploració per autor "Moll Echeto, Francisco de Borja"
Ara es mostren els items 12-31 de 98
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An on-line test strategy and analysis for a 1T1R crossbar memory
(Institute of Electrical and Electronics Engineers (IEEE), 2017)
Text en actes de congrés
Accés obertMemristors are emerging devices known by their nonvolability, compatibility with CMOS processes and high density in circuits density in circuits mostly owing to the crossbar nanoarchitecture. One of their most notable ... -
Analysis and modelling of parasitic substrate coupling in CMOS circuits
(1995-10)
Article
Accés restringit per política de l'editorialAnalysis of the substrate coupling in integrated circuits is done taking into account technology and layout parameters for different types and location of transistors using a device-level simulator. The noise coupling ... -
Analysis of body bias and RTN-induced frequency shift of low voltage ring oscillators in FDSOI technology
(Institute of Electrical and Electronics Engineers (IEEE), 2018)
Text en actes de congrés
Accés restringit per política de l'editorialElectronic circuits powered at ultra low voltages (500 mV and below) are desirable for their low energy and power consumption. However, RTN (Random Telegraph Noise)-induced threshold voltage variations become very significant ... -
Analysis of random body bias application in FDSOI cryptosystems as a countermeasure to leakage-based power analysis attacks
(Institute of Electrical and Electronics Engineers (IEEE), 2021)
Article
Accés obertThis paper analyses a novel countermeasure to Leakage Power Analysis Attacks based on the application of a random Body Bias voltage level at the beginning of the encryption process. The countermeasure effectiveness is ... -
ASIC implementation of an all-digital self-adaptive PVTA variation-aware clock generation system
(Association for Computing Machinery (ACM), 2016)
Text en actes de congrés
Accés restringit per política de l'editorialAn all-digital self-adaptive clock generation system capable of autonomously adapt the clock frequency to compensate the effects of static spatially heterogeneous (SSHet) PVTA variations is presented. The design uses ... -
Asynchronous pulse logic cell for threshold logic and Boolean networks
(Institute of Electrical and Electronics Engineers (IEEE), 2005)
Text en actes de congrés
Accés restringit per política de l'editorialIn this article, a fully digital CMOS circuit for asynchronous pulse cells is presented. The proposed circuit has a high noise tolerance and no static power consumption. Furthermore it has a high functional programmability. ... -
Body bias generators for ultra low voltage circuits in FDSOI technology
(Institute of Electrical and Electronics Engineers (IEEE), 2018)
Text en actes de congrés
Accés restringit per política de l'editorialElectronic circuits powered at ultra low voltages (300 mV and below) are desirable for their low energy and power consumption. However, the performance at such low power voltage is severely degraded. FDSOI technology, with ... -
Closed loop controlled ring oscillator: a variation tolerant self-adaptive clock generation architecture
(2012)
Comunicació de congrés
Accés obert -
Current balancing random body bias in FDSOI cryptosystems as a countermeasure to leakage power analysis attacks
(Institute of Electrical and Electronics Engineers (IEEE), 2022)
Article
Accés obertThis paper identifies vulnerabilities to recently proposed countermeasures to leakage power analysis attacks in FDSOI systems based on the application of a random body bias. The vulnerabilities are analyzed and the relative ... -
Data relevance-aware dynamic sensing technique with battery lifetime guarantee for wireless sensor nodes
(Institute of Electrical and Electronics Engineers (IEEE), 2021)
Text en actes de congrés
Accés restringit per política de l'editorialSignificant effort has been devoted to the development of dynamic monitoring techniques to exploit the temporal correlation among observations with the intention of improving the energy efficiency in wireless sensor nodes. ... -
Design and implementation of an adaptive proactive reconfiguration technique in SRAM caches
(2013)
Text en actes de congrés
Accés restringit per política de l'editorialScaling of device dimensions toward nano-scale regime has made it essential to innovate novel design techniques for improving the circuit robustness. This work proposes an implementation of adaptive proactive reconfiguration ... -
Design guidelines towards compact litho-friendly regular cells
(2011)
Text en actes de congrés
Accés obert -
Design of complex circuits using the via-configurable transistor array regular layout fabric
(IEEE Computer Society Publications, 2011)
Text en actes de congrés
Accés restringit per política de l'editorialLayout regularity will be mandatory for future CMOS technologies to mitigate manufacturability issues. However, existing CAD tools do not meet the needs imposed by regularity constraints. In this paper we present a new ... -
Diseño de circuitos y sistemas integrados
(Edicions UPC, 2000)
Llibre
Accés restringit a la comunitat UPCLa tecnología de circuitos integrados, basada principalmente en la miniaturización de los circuitos -con el incremento de prestaciones y la fuerte reducción de costos consiguientes– ha evolucionado intensamente en los ... -
Diseño de circuitos y sistemas integrados
(Edicions UPC, 2003)
Llibre
Accés restringit als usuaris de la UB, UAB, UPC, UPF, UdG, UdL, URV, UOC, BC, UVic, UJI, URL, UICLa tecnología de circuitos integrados, basada principalmente en la miniaturización de los circuitos ha evolucionado intensamente en los últimos tiempos. El objetivo de esta obra es dar a conocer esta evolución reciente y ... -
DVINO: A RISC-V vector processor implemented in 65nm technology
(Institute of Electrical and Electronics Engineers (IEEE), 2022)
Comunicació de congrés
Accés obertThis paper describes the design, verification, implementation and fabrication of the Drac Vector IN-Order (DVINO) processor, a RISC-V vector processor capable of booting Linux jointly developed by BSC, CIC-IPN, IMB-CNM ... -
Energy and relevance-aware adaptive monitoring method for wireless sensor nodes with hard energy constraints
(2024-01-01)
Article
Accés obertTraditional dynamic energy management methods optimize the energy usage in wireless sensor nodes adjusting their behavior to the operating conditions. However, this comes at the cost of losing the predictability in the ... -
Energy efficient object detection for automotive applications with YOLOv3 and approximate hardware
(Institute of Electrical and Electronics Engineers (IEEE), 2023)
Text en actes de congrés
Accés obertDeep neural networks are the dominant models for perception tasks in the automotive domain, but their high computational complexity makes it difficult to execute them in real time with an acceptable power consumption on ... -
Energy macro-model for on chip interconnection buses
(2006-06)
Report de recerca
Accés obertThis report presents a fast method of evaluating the power consumption of a bus. Given an on-chip bus driver-interconnection-receiver design of N parallel lines,the objective is to develop its energy consumption macro-model. ... -
Error probability in synchronous digital circuits due to power supply noise
(2007-09)
Text en actes de congrés
Accés obertThis paper presents a probabilistic approach to model the problem of power supply voltage fluctuations. Error probability calculations are shown for some 90-nm technology digital circuits. The analysis here considered ...
