Exploració per autor "Espasa Sans, Roger"
Ara es mostren els items 17-18 de 18
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Simultaneous multithreaded vector architecture: merging ILP and DLP for high performance
Espasa Sans, Roger; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 1997)
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Accés obertShows that instruction-level parallelism (ILP) and data-level parallelism (DLP) can be merged in a single simultaneous vector multithreaded architecture to execute regular vectorizable code at a performance level that ... -
Three-dimensional memory vectorization for high bandwidth media memory systems
Corbal San Adrián, Jesús; Espasa Sans, Roger; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2002)
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Accés obertVector processors have good performance, cost and adaptability when targeting multimedia applications. However, for a significant number of media programs, conventional memory configurations fail to deliver enough memory ...