Ara es mostren els items 11-18 de 18

    • MOM: a matrix SIMD instruction set architecture for multimedia applications 

      Corbal San Adrián, Jesús; Valero Cortés, Mateo; Espasa Sans, Roger (Institute of Electrical and Electronics Engineers (IEEE), 1999)
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      MOM is a novel matrix-oriented ISA paradigm for multimedia applications, based on fusing conventional vector ISAs with SIMD ISAs such as MMX. This paper justifies why MOM is a suitable alternative for the multimedia domain ...
    • Multithreaded vector architectures 

      Espasa Sans, Roger; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 1997)
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      The purpose of this paper is to show that multi-threading techniques can be applied to a vector processor to greatly increase processor throughput and maximize resource utilization. Using a trace driven approach, we simulate ...
    • On the efficiency of reductions in µ-SIMD media extensions 

      Corbal San Adrián, Jesús; Espasa Sans, Roger; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2001)
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      Many important multimedia applications contain a significant fraction of reduction operations. Although, in general, multimedia applications are characterized for having high amounts of Data Level Parallelism, reductions ...
    • Out-of-order vector architectures 

      Espasa Sans, Roger; Valero Cortés, Mateo; Smith, James E. (Institute of Electrical and Electronics Engineers (IEEE), 1997)
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      Register renaming and out-of-order instruction issue are now commonly used in superscalar processors. These techniques can also be used to significant advantage in vector processors, as this paper shows. Performance is ...
    • Processor Design 

      Espasa Sans, Roger; Canal Corretger, Ramon (Universitat Politècnica de Catalunya, 2017)
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    • Quantitative analysis of vector code 

      Espasa Sans, Roger; Valero Cortés, Mateo; Padua, David; Jiménez Castells, Marta; Ayguadé Parra, Eduard (Institute of Electrical and Electronics Engineers (IEEE), 1995)
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      In this paper we present the results of a detailed simulation study of the execution of vector programs on a single processor of a Convex C3480 machine, using a subset of the Perfect Club benchmarks. We are interested in ...
    • Simultaneous multithreaded vector architecture: merging ILP and DLP for high performance 

      Espasa Sans, Roger; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 1997)
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      Shows that instruction-level parallelism (ILP) and data-level parallelism (DLP) can be merged in a single simultaneous vector multithreaded architecture to execute regular vectorizable code at a performance level that ...
    • Three-dimensional memory vectorization for high bandwidth media memory systems 

      Corbal San Adrián, Jesús; Espasa Sans, Roger; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2002)
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      Vector processors have good performance, cost and adaptability when targeting multimedia applications. However, for a significant number of media programs, conventional memory configurations fail to deliver enough memory ...