Exploració per autor "Larriba Pey, Josep"Més informacióMés informació

Ara es mostren els items 33-40 de 40

    • Semantic blocking for record linkage 

      Nin Guerrero, Jordi; Muntés Mulero, Víctor; Martínez Bazán, Norbert; Larriba Pey, Josep (IOS Press, 2007)
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      Record Linkage (RL) is an important component of data cleaning and integration and data processing in general. For years, many efforts have focused on improving the performance of the RL process, either by reducing the ...

    • Social based layouts for the increase of locality in graph operations 

      Prat Pérez, Arnau; Domínguez Sal, David; Larriba Pey, Josep (2011)
      Article
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      Graphs provide a natural data representation for analyzing the relationships among entities in many application areas. Since the analysis algorithms perform memory intensive operations, it is important that the graph ...

    • Software trace cache 

      Ramírez Bellido, Alejandro; Larriba Pey, Josep; Valero Cortés, Mateo (2005-01)
      Article
      Accés obert
      We explore the use of compiler optimizations, which optimize the layout of instructions in memory. The target is to enable the code to make better use of the underlying hardware resources regardless of the specific details ...

    • The effect of code reordering on branch prediction 

      Ramírez Bellido, Alejandro; Larriba Pey, Josep; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2000)
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      Branch prediction accuracy is a very important factor for superscalar processor performance. The ability to predict the outcome of a branch allows the processor to effectively use a large instruction window, and extract a ...

    • Trace cache redundancy: red and blue traces 

      Ramírez Bellido, Alejandro; Larriba Pey, Josep; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2000)
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      The objective of this paper is to improve the use of the hardware resources of the trace cache mechanism, reducing the implementation cost with no performance degradation. We achieve that by eliminating the replication of ...

    • Transistor count and chip-space estimation of simplescalar-based microprocessor model 

      Steinhaus, Marc; Kolla, Reiner; Larriba Pey, Josep; Ungerer, Theo; Valero Cortés, Mateo (2001)
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      This paper proposes a chip space and transistor count estimation tool, which receives its input from the baseline architecture and the configuration file of the microarchitecture performance simulator sim-outorder of the ...

    • Two-way replacement selection 

      Martínez Palau, Xavier; Domínguez Sal, David; Larriba Pey, Josep (Association for Computing Machinery (ACM), 2010-09-01)
      Article
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      The performance of external sorting using merge sort is highly dependent on the length of the runs generated. One of the most commonly used run generation strategies is Replacement Selection (RS) because, on average, it ...

    • Using Evolutive Summary Counters for Efficient Cooperative Caching in Search Engines 

      Domínguez Sal, David; Aguilar Saborit, Josep; Surdeanu, Mihai; Larriba Pey, Josep (2012-04)
      Article
      Accés obert