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Ara es mostren els items 23-33 de 33

    • Optimizing program locality through CMEs and GAs 

      Vera Rivera, Francisco Javier; Abella Ferrer, Jaume; González Colás, Antonio María; Llosa Espuny, José Francisco (Institute of Electrical and Electronics Engineers (IEEE), 2003)
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      Caches have become increasingly important with the widening gap between main memory and processor speeds. Small and fast cache memories are designed to bridge this discrepancy. However, they are only effective when programs ...

    • Out-of-order commit processors 

      Cristal Kestelman, Adrián; Ortega, Daniel; Llosa Espuny, José Francisco; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2004)
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      Modern out-of-order processors tolerate long latency memory operations by supporting a large number of in-flight instructions. This is particularly useful in numerical applications where branch speculation is normally not ...

    • Performance and power evaluation of clustered VLIW processors with wide functional units 

      Pericàs Gleim, Miquel; Ayguadé Parra, Eduard; Zalamea León, Francisco Javier; Llosa Espuny, José Francisco; Valero Cortés, Mateo (2004-11)
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      Architectural resources and program recurrences are themain limitations to the amount of Instruction-Level Parallelism (ILP) exploitable from loops. To increase the number of operations per second, current designs use high ...

    • Performance evaluation of CSMT for VLIW processors 

      Gupta, Manoj; Llosa Espuny, José Francisco; Sánchez Carracedo, Fermín (2007-07)
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      Clustered VLIW embedded processors have become widespread due to benefits of simple hardware and low power. However, while some applications exhibit large amounts of instruction level parallelism (ILP) and benefit from ...

    • ¿Por qué faltan a clase los alumnos? 

      Sánchez Carracedo, Fermín; Álvarez Martínez, Carlos; Fernández Jiménez, Agustín; Llosa Espuny, José Francisco (Asociación de Enseñantes Universitarios de la Informática (AENUI), 2017)
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      Como profesores, con frecuencia hemos observado que no todos los estudiantes asisten regularmente a clase y que, en momentos puntuales del curso, una cantidad significativa de ellos desaparece de las aulas. La mayoría de ...

    • Quantitative evaluation of register pressure on software pipeline loops 

      Llosa Espuny, José Francisco; Ayguadé Parra, Eduard; Valero Cortés, Mateo (1998-02)
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      Software Pipelining is a loop scheduling technique that extracts loop parallelism by overlapping the execution of several consecutive iterations. One of the drawbacks of software pipelining is its high register requirements, ...

    • Register constrained modulo scheduling 

      Zalamea León, Francisco Javier; Llosa Espuny, José Francisco; Ayguadé Parra, Eduard; Valero Cortés, Mateo (2004-05)
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      Software pipelining is an instruction scheduling technique that exploits the instruction level parallelism (ILP) available in loops by overlapping operations from various successive loop iterations. The main drawback of ...

    • Software and hardware techniques to optimize register file utilization in VLIW 

      Zalamea León, Francisco Javier; Llosa Espuny, José Francisco; Ayguadé Parra, Eduard; Valero Cortés, Mateo (2004-12)
      Article
      Accés restringit per política de l'editorial
      High-performance microprocessors are currently designed with the purpose of exploiting instruction level parallelism (ILP). The techniques used in their design and the aggressive scheduling techniques used to exploit this ...

    • Swing modulo scheduling: a lifetime-sensitive approach 

      Llosa Espuny, José Francisco; González Colás, Antonio María; Ayguadé Parra, Eduard; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 1996)
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      This paper presents a novel software pipelining approach, which is called Swing Modulo Scheduling (SMS). It generates schedules that are near optimal in terms of initiation interval, register requirements and stage count. ...

    • Thread merging schemes for multithreaded clustered VLIW processors 

      Gupta, Manoj; Sánchez Carracedo, Fermín; Llosa Espuny, José Francisco (2009-09)
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      Several multithreading techniques have been proposed to reduce the resource underutilization in Very Long Instruction Word (VLIW) processors. Simultaneous MultiThreading (SMT) is a popular technique which improves processor ...

    • Widening resources: a cost-effective technique for aggressive ILP architectures 

      López Álvarez, David; Llosa Espuny, José Francisco; Valero Cortés, Mateo; Ayguadé Parra, Eduard (Institute of Electrical and Electronics Engineers (IEEE), 1998)
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      The inherent instruction-level parallelism (ILP) of current applications (specially those based on floating point computations) has driven hardware designers and compilers writers to investigate aggressive techniques for ...