Exploració per autor "Llosa Espuny, José Francisco"
Ara es mostren els items 16-33 de 33
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Lifetime-sensitive modulo scheduling in a production environment
(2001-03)
Article
Accés obertThis paper presents a novel software pipelining approach, which is called Swing Modulo Scheduling (SMS). It generates schedules that are near optimal in terms of initiation interval, register requirements, and stage count. ... -
Lightning talks of EduHPC 2022
(Institute of Electrical and Electronics Engineers (IEEE), 2022)
Text en actes de congrés
Accés obertThe lightning talks at EduHPC provide an opportunity to share early results and insights on parallel and distributed computing (PDC) education and training efforts. The four lightning talks at EduHPC 2022 cover a range of ... -
Mirs: modulo scheduling with integrated register spilling
(2003-01)
Article
Accés restringit per política de l'editorialThe overlapping of loop iterations in software pipelining techniques imposes high register requirements. The schedule for a loop is valid if it requires at most the number of registers available in the target architecture. ... -
Modulo scheduling with integrated register spilling for clustered VLIW architectures
(Institute of Electrical and Electronics Engineers (IEEE), 2001)
Text en actes de congrés
Accés obertClustering is a technique to decentralize the design of future wide issue VLIW cores and enable them to meet the technology constraints in terms of cycle time, area and power dissipation. In a clustered design, registers ... -
Modulo scheduling with reduced register pressure
(1998-06)
Article
Accés obertSoftware pipelining is a scheduling technique that is used by some product compilers in order to expose more instruction level parallelism out of innermost loops. Module scheduling refers to a class of algorithms for ... -
Near-optimal loop tiling by means of cache miss equations and genetic algorithms
(Institute of Electrical and Electronics Engineers (IEEE), 2002)
Text en actes de congrés
Accés obertThe effectiveness of the memory hierarchy is critical for the performance of current processors. The performance of the memory hierarchy can be improved by means of program transformations such as loop tiling, which is a ... -
Non-consistent dual register files to reduce register pressure
(Institute of Electrical and Electronics Engineers (IEEE), 1995)
Text en actes de congrés
Accés obertThe continuous grow on instruction level parallelism offered by microprocessors requires a large register file and a large number of ports to access it. This paper presents the non-consistent dual register file, an alternative ... -
Optimizing program locality through CMEs and GAs
(Institute of Electrical and Electronics Engineers (IEEE), 2003)
Text en actes de congrés
Accés obertCaches have become increasingly important with the widening gap between main memory and processor speeds. Small and fast cache memories are designed to bridge this discrepancy. However, they are only effective when programs ... -
Out-of-order commit processors
(Institute of Electrical and Electronics Engineers (IEEE), 2004)
Text en actes de congrés
Accés obertModern out-of-order processors tolerate long latency memory operations by supporting a large number of in-flight instructions. This is particularly useful in numerical applications where branch speculation is normally not ... -
Performance and power evaluation of clustered VLIW processors with wide functional units
(2004-11)
Article
Accés restringit per política de l'editorialArchitectural resources and program recurrences are themain limitations to the amount of Instruction-Level Parallelism (ILP) exploitable from loops. To increase the number of operations per second, current designs use high ... -
Performance evaluation of CSMT for VLIW processors
(2007-07)
Text en actes de congrés
Accés obertClustered VLIW embedded processors have become widespread due to benefits of simple hardware and low power. However, while some applications exhibit large amounts of instruction level parallelism (ILP) and benefit from ... -
¿Por qué faltan a clase los alumnos?
(Asociación de Enseñantes Universitarios de la Informática (AENUI), 2017)
Text en actes de congrés
Accés obertComo profesores, con frecuencia hemos observado que no todos los estudiantes asisten regularmente a clase y que, en momentos puntuales del curso, una cantidad significativa de ellos desaparece de las aulas. La mayoría de ... -
Quantitative evaluation of register pressure on software pipeline loops
(1998-02)
Article
Accés restringit per política de l'editorialSoftware Pipelining is a loop scheduling technique that extracts loop parallelism by overlapping the execution of several consecutive iterations. One of the drawbacks of software pipelining is its high register requirements, ... -
Register constrained modulo scheduling
(2004-05)
Article
Accés restringit per política de l'editorialSoftware pipelining is an instruction scheduling technique that exploits the instruction level parallelism (ILP) available in loops by overlapping operations from various successive loop iterations. The main drawback of ... -
Software and hardware techniques to optimize register file utilization in VLIW
(2004-12)
Article
Accés restringit per política de l'editorialHigh-performance microprocessors are currently designed with the purpose of exploiting instruction level parallelism (ILP). The techniques used in their design and the aggressive scheduling techniques used to exploit this ... -
Swing modulo scheduling: a lifetime-sensitive approach
(Institute of Electrical and Electronics Engineers (IEEE), 1996)
Text en actes de congrés
Accés obertThis paper presents a novel software pipelining approach, which is called Swing Modulo Scheduling (SMS). It generates schedules that are near optimal in terms of initiation interval, register requirements and stage count. ... -
Thread merging schemes for multithreaded clustered VLIW processors
(2009-09)
Comunicació de congrés
Accés obertSeveral multithreading techniques have been proposed to reduce the resource underutilization in Very Long Instruction Word (VLIW) processors. Simultaneous MultiThreading (SMT) is a popular technique which improves processor ... -
Widening resources: a cost-effective technique for aggressive ILP architectures
(Institute of Electrical and Electronics Engineers (IEEE), 1998)
Text en actes de congrés
Accés obertThe inherent instruction-level parallelism (ILP) of current applications (specially those based on floating point computations) has driven hardware designers and compilers writers to investigate aggressive techniques for ...
