Exploració per autor "Llosa Espuny, José Francisco"
Ara es mostren els items 6-25 de 33
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Cost-conscious strategies to increase performance of numerical programs on agressive VLIW architectures
López Álvarez, David; Llosa Espuny, José Francisco; Valero Cortés, Mateo; Ayguadé Parra, Eduard (2001-10)
Article
Accés obertLoops are the main time-consuming part of numerical applications. The performance of the loops is limited either by the resources offered by the architecture or by recurrences in the computation. To execute more operations ... -
El impacto de eliminar el examen final
Llosa Espuny, José Francisco; Álvarez Martínez, Carlos; Fernández Jiménez, Agustín; Sánchez Carracedo, Fermín (2016-09)
Article
Accés obertDesde hace algún tiempo se publican en JENUI artículos donde se argumenta sobre la conveniencia de eliminar el examen final como forma de fomentar el trabajo del estudiante durante todo el curso. Convencidos de lo apropiado ... -
Evaluación formativa con feedback rápido usando mandos interactivos
Álvarez Martínez, Carlos; Llosa Espuny, José Francisco (Universidade de Santiago de Compostela. Escola Técnica Superior d'Enxeñaría, 2010-07-07)
Comunicació de congrés
Accés obertNumerosos estudios han demostrado que el uso del feedback como herramienta docente resulta beneficioso para el aprendizaje. Para que este feedback sea útil debe ser rápido, es decir, llegar al alumno poco después de ... -
Heuristics for register-constrained software pipelining
Llosa Espuny, José Francisco; Valero Cortés, Mateo; Ayguadé Parra, Eduard (Institute of Electrical and Electronics Engineers (IEEE), 1996)
Text en actes de congrés
Accés obertSoftware Pipelining is a loop scheduling technique that extracts parallelism from loops by overlapping the execution of several consecutive iterations. There has been a significant effort to produce throughput-optimal ... -
Hierarchical clustered register file organization for VLIW processors
Zalamea León, Francisco Javier; Llosa Espuny, José Francisco; Ayguadé Parra, Eduard; Valero Cortés, Mateo (IEEE Computer Society, 2003)
Text en actes de congrés
Accés obertTechnology projections indicate that wire delays will become one of the biggest constraints in future microprocessor designs. To avoid long wire delays and therefore long cycle times, processor cores must be partitioned ... -
Hybrid multithreading for VLIW processors
Gupta, Manoj; Sánchez Carracedo, Fermín; Llosa Espuny, José Francisco (2009-10)
Text en actes de congrés
Accés obertSeveral multithreading techniques have been proposed to reduce resource underutilization in Very Long Instruction Word (VLIW) processors. Simultaneous MultiThreading (SMT) is a popular technique that improves processor ... -
Hypernode reduction modulo scheduling
Llosa Espuny, José Francisco; Valero Cortés, Mateo; Ayguadé Parra, Eduard; González Colás, Antonio María (Institute of Electrical and Electronics Engineers (IEEE), 1995)
Text en actes de congrés
Accés obertSoftware pipelining is a loop scheduling technique that extracts parallelism from loops by overlapping the execution of several consecutive iterations. Most prior scheduling research has focused on achieving minimum execution ... -
Impact on performance of fused multiply-add units in aggressive VLIW architectures
López Álvarez, David; Llosa Espuny, José Francisco; Ayguadé Parra, Eduard; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 1999)
Text en actes de congrés
Accés obertLoops are the main time consuming part of programs based on floating point computations. The performance of the loops is limited either by recurrences in the computation or by the resources offered by the architecture. ... -
El Impacto de eliminar el examen final
Llosa Espuny, José Francisco; Álvarez Martínez, Carlos; Fernández Jiménez, Agustín; Sánchez Carracedo, Fermín (Universidad de Almería, 2016-07-06)
Comunicació de congrés
Accés obertDesde hace algún tiempo se publican en JENUI artículos donde se argumenta sobre la conveniencia de eliminar el examen final como forma de fomentar el trabajo del estudiante durante todo el curso. Convencidos de lo apropiado ... -
Incorporació de sistemes de resposta interactiva a la docència presencial
Sánchez Carracedo, Fermín; Fonseca, Pau; Delgado Mercè, Jaime; Llorente Viejo, Silvia; Cerda, Llorenç; Llosa Espuny, José Francisco; Álvarez, Carlos; Sesé Castel, Gemma; Bravo Amella, Hector; Moralhelche Piulachs, Jordi (Universitat Politècnica de Catalunya. Institut de Ciències de l'Educació, 2010-02-11)
Comunicació de congrés / Text en actes de congrés
Accés obertAquest projecte, de Suport a la Docència, consisteix en la incorporació d’uns comandaments amb botons del 0 al 9 a les classes per tal de donar suport als professors a les seves classes i, d’aquesta manera, avaluar els ... -
Lifetime-sensitive modulo scheduling in a production environment
Llosa Espuny, José Francisco; Ayguadé Parra, Eduard; González Colás, Antonio María; Valero Cortés, Mateo; Eckhardt, Jason (2001-03)
Article
Accés obertThis paper presents a novel software pipelining approach, which is called Swing Modulo Scheduling (SMS). It generates schedules that are near optimal in terms of initiation interval, register requirements, and stage count. ... -
Lightning talks of EduHPC 2022
Qasem, Apan; Anzt, Hartwig; Ayguadé Parra, Eduard; Cahil, Katharine; Canal Corretger, Ramon; Chan, Jany; Fosler-Lussier, Eric; Llosa Espuny, José Francisco; Martorell Bofill, Xavier; Sancho Samsó, María Ribera (Institute of Electrical and Electronics Engineers (IEEE), 2022)
Text en actes de congrés
Accés obertThe lightning talks at EduHPC provide an opportunity to share early results and insights on parallel and distributed computing (PDC) education and training efforts. The four lightning talks at EduHPC 2022 cover a range of ... -
Mirs: modulo scheduling with integrated register spilling
Zalamea León, Francisco Javier; Llosa Espuny, José Francisco; Ayguadé Parra, Eduard; Valero Cortés, Mateo (2003-01)
Article
Accés restringit per política de l'editorialThe overlapping of loop iterations in software pipelining techniques imposes high register requirements. The schedule for a loop is valid if it requires at most the number of registers available in the target architecture. ... -
Modulo scheduling with integrated register spilling for clustered VLIW architectures
Zalamea León, Francisco Javier; Llosa Espuny, José Francisco; Ayguadé Parra, Eduard; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2001)
Text en actes de congrés
Accés obertClustering is a technique to decentralize the design of future wide issue VLIW cores and enable them to meet the technology constraints in terms of cycle time, area and power dissipation. In a clustered design, registers ... -
Modulo scheduling with reduced register pressure
Llosa Espuny, José Francisco; Valero Cortés, Mateo; Ayguadé Parra, Eduard; González Colás, Antonio María (1998-06)
Article
Accés obertSoftware pipelining is a scheduling technique that is used by some product compilers in order to expose more instruction level parallelism out of innermost loops. Module scheduling refers to a class of algorithms for ... -
Near-optimal loop tiling by means of cache miss equations and genetic algorithms
Abella Ferrer, Jaume; González Colás, Antonio María; Llosa Espuny, José Francisco; Vera Rivera, Francisco Javier (Institute of Electrical and Electronics Engineers (IEEE), 2002)
Text en actes de congrés
Accés obertThe effectiveness of the memory hierarchy is critical for the performance of current processors. The performance of the memory hierarchy can be improved by means of program transformations such as loop tiling, which is a ... -
Non-consistent dual register files to reduce register pressure
Llosa Espuny, José Francisco; Valero Cortés, Mateo; Ayguadé Parra, Eduard (Institute of Electrical and Electronics Engineers (IEEE), 1995)
Text en actes de congrés
Accés obertThe continuous grow on instruction level parallelism offered by microprocessors requires a large register file and a large number of ports to access it. This paper presents the non-consistent dual register file, an alternative ... -
Optimizing program locality through CMEs and GAs
Vera Rivera, Francisco Javier; Abella Ferrer, Jaume; González Colás, Antonio María; Llosa Espuny, José Francisco (Institute of Electrical and Electronics Engineers (IEEE), 2003)
Text en actes de congrés
Accés obertCaches have become increasingly important with the widening gap between main memory and processor speeds. Small and fast cache memories are designed to bridge this discrepancy. However, they are only effective when programs ... -
Out-of-order commit processors
Cristal Kestelman, Adrián; Ortega, Daniel; Llosa Espuny, José Francisco; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2004)
Text en actes de congrés
Accés obertModern out-of-order processors tolerate long latency memory operations by supporting a large number of in-flight instructions. This is particularly useful in numerical applications where branch speculation is normally not ... -
Performance and power evaluation of clustered VLIW processors with wide functional units
Pericàs Gleim, Miquel; Ayguadé Parra, Eduard; Zalamea León, Francisco Javier; Llosa Espuny, José Francisco; Valero Cortés, Mateo (2004-11)
Article
Accés restringit per política de l'editorialArchitectural resources and program recurrences are themain limitations to the amount of Instruction-Level Parallelism (ILP) exploitable from loops. To increase the number of operations per second, current designs use high ...