Exploració per autor "Rubio Sola, Jose Antonio"
Ara es mostren els items 139-158 de 175
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SET and noise fault tolerant circuit design techniques: application to 7 nm FinFET
(2014-04-01)
Article
Accés obertIn the near future of high component density and low-power technologies, soft errors occurring not only in memory systems and latches but also in the combinational parts of logic circuits will seriously affect the reliable ... -
Shape effects on electromigration in VLSI interconnects
(1997-07)
Article
Accés restringit per política de l'editorialThe influence of the shape of VLSI interconnects on the lifetime due to electromigration is investigated. Simulations and experiments indicate that, in some cases, the right angle corners of the metal lines, widely ... -
Shape-shifting digital hardware concept: towards a new adaptive computing system
(IEEE Press. Institute of Electrical and Electronics Engineers, 2012)
Comunicació de congrés
Accés restringit per política de l'editorialIn this paper a new approach to implement adaptive hardware (AH) based on memFETs crossbar structure is presented. We report a novel computing hardware principle called Shape-Shifting Digital Hardware (SSDH) oriented ... -
Shortest path computing in directed graphs with weighted edges mapped on random networks of memristors
(2020-03-01)
Article
Accés obertTo accelerate the execution of advanced computing tasks, in-memory computing with resistive memory provides a promising solution. In this context, networks of memristors could be used as parallel computing medium for the ... -
Sistema gràfic interactiu per al disseny semi custom de circuits integrats
(Universitat Politècnica de Barcelona. Centre de Càlcul, 1986-09)
Article
Accés obertDes de l'introducció dels Circuits Integrats als anys 60, les industries electròniques han experimentat un rapidissim desenvolupament. Tant els dissenyadors de les petites industries com els de les grans companyies ... -
SRAM lifetime improvement by using adaptive proactive reconfiguration
(IEEE Press. Institute of Electrical and Electronics Engineers, 2012)
Text en actes de congrés
Accés restringit per política de l'editorialModern generations of CMOS technology nodes are facing critical causes of hardware reliability failures, which were not significant in the past. Such vulnerabilities make it essential to investigate new robust design ... -
Statistical analysis and comparison of 2T and 3T1D e-DRAM minimum energy operation
(2017-03-01)
Article
Accés obertBio-medical wearable devices restricted to their small-capacity embedded-battery require energy-efficiency of the highest order. However, minimum-energy point (MEP) at sub-threshold voltages is unattainable with SRAM memory, ... -
Statistical analysis and comparison of 2T and 3T1D e-DRAM minimum energy operation
(Institute of Electrical and Electronics Engineers (IEEE), 2016)
Text en actes de congrés
Accés obertBio-medical wearable devices restricted to their small-capacity embedded-battery require energy-efficiency of the highest order. However, minimum-energy point (MEP) at sub-threshold voltages is unattainable with SRAM memory, ... -
Statistical characterization and modeling of random telegraph noise effects in 65nm SRAM cells
(Institute of Electrical and Electronics Engineers (IEEE), 2017)
Text en actes de congrés
Accés restringit per política de l'editorialRandom Telegraph Noise (RTN) effects are investigated in 65nm SRAM cells by using a new characterization method that provides a significant measurement time reduction. The variability induced in commercial SRAM cells is ... -
Statistical Lifetime Analysis in Memristive Crossbar
(2015)
Text en actes de congrés
Accés obertEmerging devices for future memory technologies have attracted great attention recently. Memristors are one of the most favorable such devices, due to their high scalability and compatibility with CMOS fabrication process. ... -
Statistical lifetime analysis of memristive crossbar matrix
(Institute of Electrical and Electronics Engineers (IEEE), 2015)
Text en actes de congrés
Accés obertMemristors are considered one of the most favorable emerging device alternatives for future memory technologies. They are attracting great attention recently, due to their high scalability and compatibility with CMOS ... -
Stochastic resonance effect in binary STDP performed by RRAM devices
(Institute of Electrical and Electronics Engineers (IEEE), 2022)
Text en actes de congrés
Accés obertThe beneficial role of noise in the binary spike time dependent plasticity (STDP) learning rule, when implemented with memristors, is experimentally analyzed. The two memristor conductance states, which emulate the neuron ... -
Stochastic resonance exploration in current-driven ReRAM devices
(Institute of Electrical and Electronics Engineers (IEEE), 2022)
Text en actes de congrés
Accés obertAdvances in emerging resistive random-access memory (ReRAM) technology show promise for its use in future computing systems, enabling neuromorphic and memory-centric computing architectures. However, one aspect that holds ... -
Strategies to enhance the 3T1D-DRAM cell variability robustness beyond 22 nm
(2014-10-01)
Article
Accés obert3T1D cell has been stated as a valid alternative to be implemented on L1 memory cache to substitute 6T, highly affected by device variability as technology dimensions are reduced. In this work, we have shown that 22 nm ... -
Study on the optimal distribution of redundancy effort in cross-layer reliable architectures
(Institute of Electrical and Electronics Engineers (IEEE), 2013)
Text en actes de congrés
Accés restringit per política de l'editorialThis paper presents a comprehensive approach to the smart application of redundancy techniques in multiple-layer hierarchical systems. Computing systems today are rapidly evolving into increasingly complex structures with ... -
Suitability of FinFET introduction into eDRAM cells for operate at sub-threshold level
(Institute of Electrical and Electronics Engineers (IEEE), 2017)
Comunicació de congrés
Accés restringit per política de l'editorialThis paper explores the feasibility, in terms of performance and reliability, of gain-cell embedded DRAM (eDRAM) to be operative at sub-threshold range, when they are implemented with 10 nm FinFET devices. The use of ... -
Systematic and random variability analysis of two different 6T-SRAM layout topologies
(2013-09)
Article
Accés obert -
Tcmos: low noise power supply technique for digital ics
(1995-08)
Article
Accés obertMixed signal circuits have become an important trend in IC design. In these circuits, the effect of digital noise on the analogue part of the circuit is one of the most important performance constraints. The authors ... -
Technological layer
(The Institution of Engineering and Technology, 2020-10)
Capítol de llibre
Accés restringit per política de l'editorialThis chapter describes the fundamental characteristics of Complementary Metal-Oxide-Semiconductor (CMOS) technology, and how it can be assessed for system reliability studies. After some definitions, the dominating ... -
Temperature sensors and measurements to test analogue circuits: questions and answers
(Institute of Electrical and Electronics Engineers (IEEE), 2016)
Text en actes de congrés
Accés restringit per política de l'editorialWe have been working in the field of temperature sensors and temperature measurements to test analogue circuits during the past 10 years. As we have presented different works in many conferences, we have collected many ...
