Exploració per autor "Rubio Sola, Jose Antonio"
Ara es mostren els items 130-149 de 175
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Reliability and performance tunable architecture: the partially asynchronous R-Fold modular redundancy (pA-RMR)
(2014-04-02)
Article
Accés restringit per política de l'editorialThe R-fold modular redundancy (RMR) is a widely known fault-tolerant architecture based on hardware redundancy. It improves the system reliability by replicating the basic computing element and combining all the results ... -
Reliability challenges in design of memristive memories
(2014)
Text en actes de congrés
Accés obert -
Reliability issues in RRAM ternary memories affected by variability and aging mechanisms
(Institute of Electrical and Electronics Engineers (IEEE), 2017)
Text en actes de congrés
Accés obertResistive switching Random Access Memories (RRAM) are being considered as a promising alternative for conventional memories mainly due to their high speed, scalability, CMOS compatibility, Non-Volatile behavior (NVM), and ... -
Reliability study on technology trends beyond 20nm
(Lodz University of Technology, 2013)
Text en actes de congrés
Accés restringit per política de l'editorialIn this work, an assessment of different technology trends (planar CMOS, FinFET and III-V MOSFETs) has been carried out in front of some different reliability scenarios (variability and soft errors). The logic circuits ... -
Resistive random access memory variability and its mitigation schemes
(2017-03-01)
Article
Accés restringit per política de l'editorialThe need for design of new computing and storage paradigms has leaded to the emergence of new technologies and procedures. Among these technologies, emerging non-volatile memories such as RRAMs are getting intense attention ... -
Resistive switching behavior seen from the energy point of view
(Institute of Electrical and Electronics Engineers (IEEE), 2018)
Text en actes de congrés
Accés obertThe technology of Resistive Switching (RS) devices (memristors) is continuously maturing on its way towards viable commercial establishment. So far, the change of resistance has been identified as a function of the applied ... -
Review on suitable eDRAM configurations for next nano-metric electronics era
(2018-03)
Article
Accés obertWe summarize most of our studies focused on the main reliability issues that can threat the gain-cells eDRAM behavior when it is simulated at the nano-metric device range has been collected in this review. So, to outperform ... -
Robust sequential circuits design technique for low voltage and high noise scenarios
(2016)
Text en actes de congrés
Accés obertAll electronic processing components in future deep nanotechnologies will exhibit high noise level and/ or low S/N ratios because of the extreme voltage reduction and the nearly erratic nature of such devices. ... -
RRAM variability and its mitigation schemes
(2016)
Text en actes de congrés
Accés obertEmerging technologies such as RRAMs are attracting significant attention due to their tempting characteristics such as high scalability, CMOS compatibility and non-volatility to replace the current conventional memories. ... -
SET and noise fault tolerant circuit design techniques: application to 7 nm FinFET
(2014-04-01)
Article
Accés obertIn the near future of high component density and low-power technologies, soft errors occurring not only in memory systems and latches but also in the combinational parts of logic circuits will seriously affect the reliable ... -
Shape effects on electromigration in VLSI interconnects
(1997-07)
Article
Accés restringit per política de l'editorialThe influence of the shape of VLSI interconnects on the lifetime due to electromigration is investigated. Simulations and experiments indicate that, in some cases, the right angle corners of the metal lines, widely ... -
Shape-shifting digital hardware concept: towards a new adaptive computing system
(IEEE Press. Institute of Electrical and Electronics Engineers, 2012)
Comunicació de congrés
Accés restringit per política de l'editorialIn this paper a new approach to implement adaptive hardware (AH) based on memFETs crossbar structure is presented. We report a novel computing hardware principle called Shape-Shifting Digital Hardware (SSDH) oriented ... -
Shortest path computing in directed graphs with weighted edges mapped on random networks of memristors
(2020-03-01)
Article
Accés obertTo accelerate the execution of advanced computing tasks, in-memory computing with resistive memory provides a promising solution. In this context, networks of memristors could be used as parallel computing medium for the ... -
Sistema gràfic interactiu per al disseny semi custom de circuits integrats
(Universitat Politècnica de Barcelona. Centre de Càlcul, 1986-09)
Article
Accés obertDes de l'introducció dels Circuits Integrats als anys 60, les industries electròniques han experimentat un rapidissim desenvolupament. Tant els dissenyadors de les petites industries com els de les grans companyies ... -
SRAM lifetime improvement by using adaptive proactive reconfiguration
(IEEE Press. Institute of Electrical and Electronics Engineers, 2012)
Text en actes de congrés
Accés restringit per política de l'editorialModern generations of CMOS technology nodes are facing critical causes of hardware reliability failures, which were not significant in the past. Such vulnerabilities make it essential to investigate new robust design ... -
Statistical analysis and comparison of 2T and 3T1D e-DRAM minimum energy operation
(2017-03-01)
Article
Accés obertBio-medical wearable devices restricted to their small-capacity embedded-battery require energy-efficiency of the highest order. However, minimum-energy point (MEP) at sub-threshold voltages is unattainable with SRAM memory, ... -
Statistical analysis and comparison of 2T and 3T1D e-DRAM minimum energy operation
(Institute of Electrical and Electronics Engineers (IEEE), 2016)
Text en actes de congrés
Accés obertBio-medical wearable devices restricted to their small-capacity embedded-battery require energy-efficiency of the highest order. However, minimum-energy point (MEP) at sub-threshold voltages is unattainable with SRAM memory, ... -
Statistical characterization and modeling of random telegraph noise effects in 65nm SRAM cells
(Institute of Electrical and Electronics Engineers (IEEE), 2017)
Text en actes de congrés
Accés restringit per política de l'editorialRandom Telegraph Noise (RTN) effects are investigated in 65nm SRAM cells by using a new characterization method that provides a significant measurement time reduction. The variability induced in commercial SRAM cells is ... -
Statistical Lifetime Analysis in Memristive Crossbar
(2015)
Text en actes de congrés
Accés obertEmerging devices for future memory technologies have attracted great attention recently. Memristors are one of the most favorable such devices, due to their high scalability and compatibility with CMOS fabrication process. ... -
Statistical lifetime analysis of memristive crossbar matrix
(Institute of Electrical and Electronics Engineers (IEEE), 2015)
Text en actes de congrés
Accés obertMemristors are considered one of the most favorable emerging device alternatives for future memory technologies. They are attracting great attention recently, due to their high scalability and compatibility with CMOS ...
