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Ara es mostren els items 122-141 de 175

    • Parkinson's treatment emulation using asynchronous cellular neural networks 

      Chatzipaschalis, Ioannis; Tsakalos, Karolos-Alexandros; Sirakoulis, Georgios Ch.; Rubio Sola, Jose Antonio (Institute of Electrical and Electronics Engineers (IEEE), 2023)
      Text en actes de congrés
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      The human brain can be considered as one of the most complex systems found in nature and its underlying physical and biological mechanisms have attracted an increasing research interest especially in reference to modeling ...

    • Power supply noise and logic error probability 

      Andrade Miceli, Dennis Michael; Martorell Cid, Ferran; Pons Solé, Marc; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio (2007-08)
      Text en actes de congrés
      Accés obert
      Voltage fluctuations caused by parasitic impedances in the power supply rails of modern ICs are a major concern in nowadays ICs. The voltage fluctuations are spread out to the diverse nodes of the internal sections causing ...

    • Power-efficient noise-Induced reduction of ReRAM cell’s temporal variability effects 

      Ntinas, Vasileios; Rubio Sola, Jose Antonio; Sirakoulis, Georgios; Salvador, Emili; Pedro, Marta; Crespo-Yepes, A.; Martin Martinez, Javier; Rodríguez Martínez, Rosana; Nafría Maqueda, Montserrat (2021-04)
      Article
      Accés obert
      Resistive Random Access Memory (ReRAM) is apromising novel memory technology for non-volatile storing, with low-power operation and ultra-high area density. However, ReRAM memories still face issues through commerciali ...

    • Proactive reconfiguration, a methodology for extending SRAM lifetime 

      Pouyan, Peyman; Amat Bertran, Esteve; Rubio Sola, Jose Antonio (2012)
      Comunicació de congrés
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      The proactive reconfiguration is an emerging technique that enlarges the lifetime of memory systems with embedded SRAM cells. This work introduces a novel version that modifies and enhances the advantages of this technique ...

    • Probabilistic resistive switching device modeling based on Markov jump processes 

      Ntinas, Vasileios; Rubio Sola, Jose Antonio; Sirakoulis, Georgios (Institute of Electrical and Electronics Engineers (IEEE), 2020-12-02)
      Article
      Accés obert
      In this work, a versatile mathematical framework for multi-state probabilistic modeling of Resistive Switching (RS) devices is proposed for the first time. The mathematical formulation of memristor and Markov jump processes ...

    • Process variability in sub-16nm bulk CMOS technology 

      Rubio Sola, Jose Antonio; Figueras Pàmies, Joan; Vatajelu, Elena Ioana; Canal Corretger, Ramon (2012-03-01)
      Report de recerca
      Accés obert
      The document is part of deliverable D3.6 of the TRAMS Project (EU FP7 248789), of public nature, and shows and justifies the levels of variability used in the research project for sub-18nm bulk CMOS technologies.

    • Process variability-aware proactive reconfiguration techniques for mitigating aging effects in nano scale SRAM lifetime 

      Rubio Sola, Jose Antonio; Amat Bertran, Esteve; Pouyan, Peyman (IEEE Press. Institute of Electrical and Electronics Engineers, 2012)
      Comunicació de congrés
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      Process variations and device aging have a significant impact on the reliability and performance of nano scale integrated circuits. Proactive reconfiguration is an emerging technique to extend the lifetime of embedded ...

    • Quiescent current analysis and experimentation of defective CMOS circuits 

      Segura, J A; Champac, V H; Rodríguez Montañés, Rosa; Figueras Pàmies, Joan; Rubio Sola, Jose Antonio (1992-12)
      Article
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      Physical defects widely encountered in today's CMOS processes (bridges, gate oxide short (gas) and floating gates) are modeled taking into account the topology of the defective circuit and the parameters of the technology. ...

    • Reliability and performance tunable architecture: the partially asynchronous R-Fold modular redundancy (pA-RMR) 

      Aymerich Capdevila, Nivard; Rubio Sola, Jose Antonio (2014-04-02)
      Article
      Accés restringit per política de l'editorial
      The R-fold modular redundancy (RMR) is a widely known fault-tolerant architecture based on hardware redundancy. It improves the system reliability by replicating the basic computing element and combining all the results ...

    • Reliability challenges in design of memristive memories 

      Pouyan, Peyman; Amat, Esteve; Rubio Sola, Jose Antonio (2014)
      Text en actes de congrés
      Accés obert

    • Reliability issues in RRAM ternary memories affected by variability and aging mechanisms 

      Rubio Sola, Jose Antonio; Escudero, Manuel; Pouyan, Peyman (Institute of Electrical and Electronics Engineers (IEEE), 2017)
      Text en actes de congrés
      Accés obert
      Resistive switching Random Access Memories (RRAM) are being considered as a promising alternative for conventional memories mainly due to their high speed, scalability, CMOS compatibility, Non-Volatile behavior (NVM), and ...

    • Reliability study on technology trends beyond 20nm 

      Amat Bertran, Esteve; Calomarde Palomino, Antonio; Rubio Sola, Jose Antonio (Lodz University of Technology, 2013)
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      In this work, an assessment of different technology trends (planar CMOS, FinFET and III-V MOSFETs) has been carried out in front of some different reliability scenarios (variability and soft errors). The logic circuits ...

    • Resistive random access memory variability and its mitigation schemes 

      Pouman, Peyman; Amat Bertran, Esteve; Hamdioui, Said; Rubio Sola, Jose Antonio (2017-03-01)
      Article
      Accés restringit per política de l'editorial
      The need for design of new computing and storage paradigms has leaded to the emergence of new technologies and procedures. Among these technologies, emerging non-volatile memories such as RRAMs are getting intense attention ...

    • Resistive switching behavior seen from the energy point of view 

      Gómez Mir, Jorge Tomás; Abusleme Hoffman, Angel; Vourkas, Ioannis; Rubio Sola, Jose Antonio (Institute of Electrical and Electronics Engineers (IEEE), 2018)
      Text en actes de congrés
      Accés obert
      The technology of Resistive Switching (RS) devices (memristors) is continuously maturing on its way towards viable commercial establishment. So far, the change of resistance has been identified as a function of the applied ...

    • Review on suitable eDRAM configurations for next nano-metric electronics era 

      Amat, Esteve; Canal Corretger, Ramon; Calomarde Palomino, Antonio; Rubio Sola, Jose Antonio (2018-03)
      Article
      Accés obert
      We summarize most of our studies focused on the main reliability issues that can threat the gain-cells eDRAM behavior when it is simulated at the nano-metric device range has been collected in this review. So, to outperform ...

    • Robust sequential circuits design technique for low voltage and high noise scenarios 

      García Leyva, Lancelot; Rivera Dueñas, Juan; Calomarde Palomino, Antonio; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio (2016)
      Text en actes de congrés
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      All electronic processing components in future deep nanotechnologies will exhibit high noise level and/ or low S/N ratios because of the extreme voltage reduction and the nearly erratic nature of such devices. ...

    • RRAM variability and its mitigation schemes 

      Pouman, Peyman; Amat, Esteve; Hamdioui, Said; Rubio Sola, Jose Antonio (2016)
      Text en actes de congrés
      Accés obert
      Emerging technologies such as RRAMs are attracting significant attention due to their tempting characteristics such as high scalability, CMOS compatibility and non-volatility to replace the current conventional memories. ...

    • SET and noise fault tolerant circuit design techniques: application to 7 nm FinFET 

      Calomarde Palomino, Antonio; Amat Bertran, Esteve; Moll Echeto, Francisco de Borja; Vigara Campmany, Julio Enrique; Rubio Sola, Jose Antonio (2014-04-01)
      Article
      Accés obert
      In the near future of high component density and low-power technologies, soft errors occurring not only in memory systems and latches but also in the combinational parts of logic circuits will seriously affect the reliable ...

    • Shape effects on electromigration in VLSI interconnects 

      González Jiménez, José Luis; Rubio Sola, Jose Antonio (1997-07)
      Article
      Accés restringit per política de l'editorial
      The influence of the shape of VLSI interconnects on the lifetime due to electromigration is investigated. Simulations and experiments indicate that, in some cases, the right angle corners of the metal lines, widely ...

    • Shape-shifting digital hardware concept: towards a new adaptive computing system 

      Rubio Sola, Jose Antonio; García Almudéver, Carmen; Martin, Javier; Crespo, A.; Rodriguez, Rosa; Nafría Maqueda, Montserrat (IEEE Press. Institute of Electrical and Electronics Engineers, 2012)
      Comunicació de congrés
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      In this paper a new approach to implement adaptive hardware (AH) based on memFETs crossbar structure is presented. We report a novel computing hardware principle called Shape-Shifting Digital Hardware (SSDH) oriented ...