Exploració per autor "Rubio Sola, Jose Antonio"
Ara es mostren els items 112-131 de 175
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New redundant logic design concept for high noise and low voltage scenarios
(2011-12)
Article
Accés restringit per política de l'editorialThis paper presents a new redundant logia design concept named Turtle Logic(TL).It is a new probabilistic logic method based on port redundancy and complementary data, oriented toward emerging technologies beyond CMOS, ... -
Noise generation and coupling mechanisms in deep-submicron IC's
(2002-09)
Article
Accés obertOn-chip noise generation and coupling is an important issue in deep-submicron technologies. Advanced IC technology faces new challenges to ensure function and performance integrity. Selecting adequate test techniques ... -
Noise-induced Performance Enhancement of Variability-aware Memristor Networks
(2019)
Text en actes de congrés
Accés restringit per política de l'editorialMemristor networks are capable of low-power, massive parallel processing and information storage. Moreover, they have widely used for a vast number of intelligent data analysis applications targeting mobile edge devices ... -
Novel circuit design methodology with graphene nanoribbon based devices
(Institute of Electrical and Electronics Engineers (IEEE), 2023)
Text en actes de congrés
Accés obertGraphene has attracted a high amount of interest in recent years in many research fields, including the field of electronics. Due to its spectacular properties, it is investigated as a candidate material for the realization ... -
Novel redundant logic design for noisy low voltage scenarios
(2013)
Text en actes de congrés
Accés restringit per política de l'editorialThe concept worked in this paper named Turtle Logic (TL) is a probabilistic logic method based on port redundancy and complementary data, oriented to emerging CMOS technologies and beyond, where the thermal noise could be ... -
On evaluating temperature as observable for CMOS technology variability
(2010-05-26)
Text en actes de congrés
Accés obertThe temperature at surface of a silicon die depends on the activity of the circuits placed on it. In this paper, it is analyzed how Process, Voltage and Temperature (PVT) variations affect simultaneously some figures ... -
On the development of prognostics and system health management (PHM) techniques for ReRAM applications
(Institute of Electrical and Electronics Engineers (IEEE), 2023)
Text en actes de congrés
Accés obertThe resistive switching (RS) technology has many promising applications, but the inherent variability of RS devices has been an important obstacle for the progress towards mass production. Nonidealities of device switching ... -
On the effectiveness of hybrid mechanisms on reduction of parametric failures in caches
(2011-12-05)
Report de recerca
Accés restringit per política de l'editorialIn this paper, we provide an insight on the different proactive read/write assist methods (wordline boosting & adaptive body biasing) that help in preventing (and reducing) parametric failures when coupled with reactive ... -
On the variability-aware design of memristor-based logic circuits
(Institute of Electrical and Electronics Engineers (IEEE), 2018)
Text en actes de congrés
Accés obertEver since the advent of the first TiO 2 -based memristor and the respective linear model published by Hewlett-Packard Labs, several behavioral models of memristors have been published. Such models capture the fundamental ... -
Optimization of FinFET-based gain cells for low power sub-vt embedded drams
(2018-06-01)
Article
Accés obertSub-threshold circuits (sub-V T) are a promising alternative in the implementation of low power electronics. The implementation of gain-cell embedded DRAMs (eDRAMs) based on FinFET devices requires a careful design to ... -
Parkinson's treatment emulation using asynchronous cellular neural networks
(Institute of Electrical and Electronics Engineers (IEEE), 2023)
Text en actes de congrés
Accés restringit per política de l'editorialThe human brain can be considered as one of the most complex systems found in nature and its underlying physical and biological mechanisms have attracted an increasing research interest especially in reference to modeling ... -
Power supply noise and logic error probability
(2007-08)
Text en actes de congrés
Accés obertVoltage fluctuations caused by parasitic impedances in the power supply rails of modern ICs are a major concern in nowadays ICs. The voltage fluctuations are spread out to the diverse nodes of the internal sections causing ... -
Power-efficient noise-Induced reduction of ReRAM cell’s temporal variability effects
(2021-04)
Article
Accés obertResistive Random Access Memory (ReRAM) is apromising novel memory technology for non-volatile storing, with low-power operation and ultra-high area density. However, ReRAM memories still face issues through commerciali ... -
Proactive reconfiguration, a methodology for extending SRAM lifetime
(2012)
Comunicació de congrés
Accés restringit per política de l'editorialThe proactive reconfiguration is an emerging technique that enlarges the lifetime of memory systems with embedded SRAM cells. This work introduces a novel version that modifies and enhances the advantages of this technique ... -
Probabilistic resistive switching device modeling based on Markov jump processes
(Institute of Electrical and Electronics Engineers (IEEE), 2020-12-02)
Article
Accés obertIn this work, a versatile mathematical framework for multi-state probabilistic modeling of Resistive Switching (RS) devices is proposed for the first time. The mathematical formulation of memristor and Markov jump processes ... -
Process variability in sub-16nm bulk CMOS technology
(2012-03-01)
Report de recerca
Accés obertThe document is part of deliverable D3.6 of the TRAMS Project (EU FP7 248789), of public nature, and shows and justifies the levels of variability used in the research project for sub-18nm bulk CMOS technologies. -
Process variability-aware proactive reconfiguration techniques for mitigating aging effects in nano scale SRAM lifetime
(IEEE Press. Institute of Electrical and Electronics Engineers, 2012)
Comunicació de congrés
Accés restringit per política de l'editorialProcess variations and device aging have a significant impact on the reliability and performance of nano scale integrated circuits. Proactive reconfiguration is an emerging technique to extend the lifetime of embedded ... -
Quiescent current analysis and experimentation of defective CMOS circuits
(1992-12)
Article
Accés restringit per política de l'editorialPhysical defects widely encountered in today's CMOS processes (bridges, gate oxide short (gas) and floating gates) are modeled taking into account the topology of the defective circuit and the parameters of the technology. ... -
Reliability and performance tunable architecture: the partially asynchronous R-Fold modular redundancy (pA-RMR)
(2014-04-02)
Article
Accés restringit per política de l'editorialThe R-fold modular redundancy (RMR) is a widely known fault-tolerant architecture based on hardware redundancy. It improves the system reliability by replicating the basic computing element and combining all the results ... -
Reliability challenges in design of memristive memories
(2014)
Text en actes de congrés
Accés obert
