Exploració per autor "Rubio Sola, Jose Antonio"
Ara es mostren els items 84-103 de 175
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Impact of adaptive proactive reconfiguration technique on Vmin and lifetime of SRAM caches
(2014)
Text en actes de congrés
Accés obertThis work presents a test and measurement technique to monitor aging and process variation status of SRAM cells as an aging-aware design technique. We have then verified our technique with an implemented chip. The obtained ... -
Impact of finfet and III-V/Ge technology on logic and memory cell behavior
(2013-11-20)
Article
Accés restringit per política de l'editorialIn this work, we assess the performance of a ring oscillator and a DRAM cell when they are implemented with different technologies (planar CMOS, FinFET and III-V MOSFETs), and subjected to different reliability scenarios ... -
Impact of positive bias temperature instability (PBTI)
(2011)
Text en actes de congrés
Accés restringit per política de l'editorialMemory circuits are playing a key role in complex multicore systems with both data and instructions storage and mailbox communication functions. There is a general concern that conventional SRAM cell based on the 6T structure ... -
Implementation of a 5x5 trits multiplier in a quasi-adiabatic ternary CMOS logic
(Institute of Electrical and Electronics Engineers (IEEE), 1997)
Text en actes de congrés
Accés obertAdiabatic switching is one technique to design low power digital IC. In order to diminish its expensive silicon area requirements an adiabatic ternary logic is proposed. A 5×5 trits (ternary signals) multiplier has been ... -
Influence of punch trough stop layer and well depths on the robustness of bulk FinFETs to heavy ions impact
(Institute of Electrical and Electronics Engineers (IEEE), 2022-05-02)
Article
Accés obertThis study analyzes the effects of the punch-through stop (PTS) layer and well depth in a bulk FinFET SRAM cell on the fraction of charge generated by an ion impact that is collected by the FinFET channel. More than 1700 ... -
INFORMER: an integrated framework for early-stage memory robustness analysis
(European Interactive Digital Advertising Alliance (EDAA), 2014)
Text en actes de congrés
Accés restringit per política de l'editorialWith the growing importance of parametric (process and environmental) variations in advanced technologies, it has become a serious challenge to design reliable, fast and low-power embedded memories. Adopting a variation-aware ... -
Insights to memristive memory cell from a reliability perspective
(Institute of Electrical and Electronics Engineers (IEEE), 2015)
Text en actes de congrés
Accés obertThe scaling roadmap of devices under a more than Moore scenario is resulting in the emergence of new types of devices. Among them, memristors seem to be promising candidates to be suitable for various areas of application ... -
Introduction to VHDL I
(2020-09-22)
Audiovisual
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Introduction to VHDL II
(2020-09-22)
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Introduction to VHDL III
(2020-09-22)
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Introduction to VHDL IV
(2020-09-22)
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Introduction to VHDL V
(2020-09-22)
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Introduction to VHDL VI
(2020-09-22)
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Introduction to VHDL VII
(2020-09-22)
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Introduction to VHDL VIII
(2020-09-22)
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iRMW: A low-cost technique to reduce NBTI-dependent parametric failures in L1 data caches
(Institute of Electrical and Electronics Engineers (IEEE), 2014)
Text en actes de congrés
Accés obertNegative bias temperature instability (NBTI) is a major cause of concern for chip designers because of its inherent ability to drastically reduce silicon reliability over the lifetime of the processor. Coupled with statistical ... -
L'EDIF, un format estàndar per a l'intercanvi de dades de dissenys electrònics
(Universitat Politècnica de Barcelona. Centre de Càlcul, 1987)
Article
Accés obertEn estos últimos años, el rápido incremento de los sistemas CAE/CAD en el campo de la electrónica ha hecho que la transferencia de información de unos sistemas a otros fuese un problema creciente. En consecuencia, se ha ... -
Manufacturing variability analysis in carbon nanotube technology: a comparison with bulk CMOS in 6T SRAM scenario
(2011)
Text en actes de congrés
Accés restringit per política de l'editorialIn silicon bulk CMOS technology the variability of the device parameters is a key drawback that may be a limiting factor for further miniaturizing nodes. New nanoscale beyond-CMOS devices are being studied such as carbon ... -
MemCA: all-memristor design for deterministic and probabilistic cellular automata hardware realization
(Institute of Electrical and Electronics Engineers (IEEE), 2023-05-08)
Article
Accés obertInspired by the behavior of natural systems, Cellular Automata (CA) tackle the demanding long-distance information transfer of conventional computers by the massive parallel computation performed by a set of locally-coupled ... -
Memristive cellular automata for modeling of epileptic brain activity
(2018)
Text en actes de congrés
Accés obertCellular Automata (CA) is a nature-inspired and widespread computational model which is based on the collective and emergent parallel computing capability of units (cells) locally interconnected in an abstract brain-like ...
