Exploració per autor "Rubio Sola, Jose Antonio"
Ara es mostren els items 81-100 de 175
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Hardware design of memristor-based oscillators for emulation of neurological diseases
Chatzipaschalis, Ioannis; Tsipas, Evangelos; Tsakalos, Karolos-Alexandros; Rubio Sola, Jose Antonio; Sirakoulis, Georgios Ch. (Institute of Electrical and Electronics Engineers (IEEE), 2023)
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Accés restringit per política de l'editorialOne of the most prominent examples of a complex system in nature is the nervous system, which exhibits oscillation phenomena across its structures, from single neurons to sophisticated neural networks. Memristors have been ... -
Heterogeneous memristive crossbar for in-memory computing
Papandroulidakis, Georgios; Vourkas, Ioanis; Sirakoulis, Georgios Ch.; Rubio Sola, Jose Antonio (Institute of Electrical and Electronics Engineers (IEEE), 2015)
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Accés obertIt's been quite a while since scientists are seeking for the ancestor of von Neumann computing architecture. Among the most promising candidates, memristor demonstrates advantageous characteristics, which open new pathways ... -
High level spectral-based análisis of power concumption in DSP's systems
Calomarde Palomino, Antonio; Mateo Peña, Diego; Rubio Sola, Jose Antonio (Institute of Electrical and Electronics Engineers (IEEE), 2006)
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Accés restringit per política de l'editorialIn this paper, an efficient technique to evaluate temporal correlation and transition activity at high level in DSP systems is presented. The method is based on the spectral distribution of signals and has the advantage ... -
Impact of adaptive proactive reconfiguration technique on Vmin and lifetime of SRAM caches
Pouyan, Peyman; Amat Bertran, Esteve; Barajas Ojeda, Enrique; Rubio Sola, Jose Antonio (2014)
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Accés obertThis work presents a test and measurement technique to monitor aging and process variation status of SRAM cells as an aging-aware design technique. We have then verified our technique with an implemented chip. The obtained ... -
Impact of finfet and III-V/Ge technology on logic and memory cell behavior
Amat Bertran, Esteve; Calomarde Palomino, Antonio; García Almudéver, Carmen; Aymerich Capdevila, Nivard; Canal Corretger, Ramon; Rubio Sola, Jose Antonio (2013-11-20)
Article
Accés restringit per política de l'editorialIn this work, we assess the performance of a ring oscillator and a DRAM cell when they are implemented with different technologies (planar CMOS, FinFET and III-V MOSFETs), and subjected to different reliability scenarios ... -
Impact of positive bias temperature instability (PBTI)
Aymerich Capdevila, Nivard; Ganapathy, Shrikanth; Rubio Sola, Jose Antonio; Canal Corretger, Ramon; González Colás, Antonio María (2011)
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Accés restringit per política de l'editorialMemory circuits are playing a key role in complex multicore systems with both data and instructions storage and mailbox communication functions. There is a general concern that conventional SRAM cell based on the 6T structure ... -
Implementation of a 5x5 trits multiplier in a quasi-adiabatic ternary CMOS logic
Mateo Peña, Diego; Rubio Sola, Jose Antonio (Institute of Electrical and Electronics Engineers (IEEE), 1997)
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Accés obertAdiabatic switching is one technique to design low power digital IC. In order to diminish its expensive silicon area requirements an adiabatic ternary logic is proposed. A 5×5 trits (ternary signals) multiplier has been ... -
Influence of punch trough stop layer and well depths on the robustness of bulk FinFETs to heavy ions impact
Calomarde Palomino, Antonio; Manich Bou, Salvador; Rubio Sola, Jose Antonio; Gamiz, Francisco (Institute of Electrical and Electronics Engineers (IEEE), 2022-05-02)
Article
Accés obertThis study analyzes the effects of the punch-through stop (PTS) layer and well depth in a bulk FinFET SRAM cell on the fraction of charge generated by an ion impact that is collected by the FinFET channel. More than 1700 ... -
INFORMER: an integrated framework for early-stage memory robustness analysis
Ganapathy, Shrikanth; Canal Corretger, Ramon; Alexandrescu, Dan; Costenaro, Eric; González Colás, Antonio María; Rubio Sola, Jose Antonio (European Interactive Digital Advertising Alliance (EDAA), 2014)
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Accés restringit per política de l'editorialWith the growing importance of parametric (process and environmental) variations in advanced technologies, it has become a serious challenge to design reliable, fast and low-power embedded memories. Adopting a variation-aware ... -
Insights to memristive memory cell from a reliability perspective
Pouyan, Peyman; Amat Bertran, Esteve; Rubio Sola, Jose Antonio (Institute of Electrical and Electronics Engineers (IEEE), 2015)
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Accés obertThe scaling roadmap of devices under a more than Moore scenario is resulting in the emergence of new types of devices. Among them, memristors seem to be promising candidates to be suitable for various areas of application ... -
Introduction to VHDL I
Altet Sanahujes, Josep; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio (2020-09-22)
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Introduction to VHDL II
Altet Sanahujes, Josep; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio (2020-09-22)
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Introduction to VHDL III
Altet Sanahujes, Josep; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio (2020-09-22)
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Introduction to VHDL IV
Altet Sanahujes, Josep; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio (2020-09-22)
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Introduction to VHDL V
Altet Sanahujes, Josep; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio (2020-09-22)
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Introduction to VHDL VI
Altet Sanahujes, Josep; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio (2020-09-22)
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Introduction to VHDL VII
Altet Sanahujes, Josep; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio (2020-09-22)
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Introduction to VHDL VIII
Altet Sanahujes, Josep; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio (2020-09-22)
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iRMW: A low-cost technique to reduce NBTI-dependent parametric failures in L1 data caches
Ganapathy, Shrikanth; Canal Corretger, Ramon; González Colás, Antonio María; Rubio Sola, Jose Antonio (Institute of Electrical and Electronics Engineers (IEEE), 2014)
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Accés obertNegative bias temperature instability (NBTI) is a major cause of concern for chip designers because of its inherent ability to drastically reduce silicon reliability over the lifetime of the processor. Coupled with statistical ... -
L'EDIF, un format estàndar per a l'intercanvi de dades de dissenys electrònics
Mir, Salvador; Mir, Xavier; Rubio Sola, Jose Antonio (Universitat Politècnica de Barcelona. Centre de Càlcul, 1987)
Article
Accés obertEn estos últimos años, el rápido incremento de los sistemas CAE/CAD en el campo de la electrónica ha hecho que la transferencia de información de unos sistemas a otros fuese un problema creciente. En consecuencia, se ha ...