Ara es mostren els items 186-192 de 192

    • Verification of asynchronous circuits by BDD-based model checking of Petri nets 

      Roig Mansilla, Oriol; Cortadella, Jordi; Pastor Llorens, Enric (Springer, 1995)
      Text en actes de congrés
      Accés obert
      This paper presents a methodology for the verification of speed-independent asynchronous circuits against a Petri net specification. The technique is based on symbolic reachability analysis, modeling both the specification ...
    • Verification of concurrent systems with parametric delays using octahedra 

      Clarisó Viladrosa, Robert; Cortadella, Jordi (Institute of Electrical and Electronics Engineers (IEEE), 2005)
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      A technique for the verification of concurrent parametric timed systems is presented. In the systems under study, each action has a bounded delay where the bounds are either constants or parameters. Given a safety property, ...
    • Verification of timed circuits with symbolic delays 

      Clarisó Viladrosa, Robert; Cortadella, Jordi (Institute of Electrical and Electronics Engineers (IEEE), 2004)
      Text en actes de congrés
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      Verifying timed circuits is a complex problem even when the delays of the system are fixed. This paper deals with a more challenging problem, the formal verification of timed circuits with unspecified delays represented ...
    • Voltage noise analysis with ring oscillator clocks 

      Machado, Lucas; Roca Pérez, Antoni; Cortadella, Jordi (Institute of Electrical and Electronics Engineers (IEEE), 2017)
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      Voltage noise is the main source of dynamic variability in integrated circuits and a major concern for the design of Power Delivery Networks (PDNs). Ring Oscillators Clocks (ROCs) have been proposed as an alternative to ...
    • Waveform Transition Graphs: a designer-friendly formalism for asynchronous behaviours 

      Cortadella, Jordi; Moreno Vega, Alberto; Sokolov, Danil; Yakovlev, Alex; Lloyd, David (Institute of Electrical and Electronics Engineers (IEEE), 2017)
      Comunicació de congrés
      Accés obert
      The paper proposes a new formal model for describing asynchronous behaviours involving the interplay of causality, concurrency and choice. The model is called Waveform Transition Graphs. Its main aim is simplifying the ...
    • What is the cost of delay insensitivity? 

      Saito, Hiroshi; Kondratyev, Alex; Cortadella, Jordi; Lavagno, Luciano; Yakovlev, Alex (Institute of Electrical and Electronics Engineers (IEEE), 1999)
      Text en actes de congrés
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      Deep submicron technology calls for new design techniques, in which wire and gate delays are accounted to have equal or nearly equal effect on circuit behaviour. Asynchronous speed-independent (SI) circuits, whose behaviour ...
    • Working-zone encoding for reducing the energy in microprocessor address buses 

      Musoll Cinca, Enric; Lang, Tomás; Cortadella, Jordi (1998-12)
      Article
      Accés obert
      The energy consumption due to input-output pins is a substantial part of the overall chip consumption. To reduce this energy, this work presents the working-zone encoding (WZE) method for encoding an external address bus, ...