Exploració per autor "Cortadella, Jordi"
Ara es mostren els items 123-142 de 192
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Narrowing the margins with elastic clocks
(Institute of Electrical and Electronics Engineers (IEEE), 2010)
Text en actes de congrés
Accés obertThe continuous shrinking of process geometries increases variability and demands for conservative margins that have a negative impact on performance. With conventional clocks, the cycle period has to be defined to accommodate ... -
New region-based algorithms for deriving bounded Petri nets
(Institute of Electrical and Electronics Engineers (IEEE), 2010-03)
Article
Accés obertThe theory of regions was introduced in the early nineties as a method to bridge state and event-based models. This paper tackles the problem of deriving a Petri net from a state-based model, using the theory of regions. ... -
On the performance evaluation of multi-guarded marked graphs with single-server semantics
(2010-09)
Article
Accés obertIn discrete event systems, a given task can start executing when all the required input data are available. The required input data for a given task may change along the evolution of the system. A way of modeling this ... -
On the realization of reactive systems
(2001-05)
Report de recerca
Accés obertA new notion of realization of reactive systems is defined. Realization is defined as a relation between the states of two transition systems, the specification and the implementation, in which events are classified as ... -
Optimizing CMOS circuits for low power using transistor reordering
(Institute of Electrical and Electronics Engineers (IEEE), 1996)
Text en actes de congrés
Accés obertThis paper addresses the optimization of a circuit for low power using transistor reordering. The optimization algorithm relies on a stochastic model of a static CMOS gate that includes the power internal nodes of the gate. ... -
Partial order based approach to synthesis of speed-independent circuits
(Institute of Electrical and Electronics Engineers (IEEE), 1997)
Text en actes de congrés
Accés obertThis paper introduces a novel technique for synthesis of speed-independent circuits from their Signal Transition Graph specifications. The new method uses partial order in the form of the STG-unfolding segment to derive ... -
Performance optimization of elastic systems using buffer resizing and buffer insertion
(Institute of Electrical and Electronics Engineers (IEEE), 2008)
Text en actes de congrés
Accés obertBuffer resizing and buffer insertion are two transformation techniques for the performance optimization of elastic systems. Different approaches for each technique have already been proposed in the literature. Both techniques ... -
Performance-preserving clustering of elastic controllers
(2008-02-15)
Report de recerca
Accés obertAsynchronous and latency-insensitive circuits offer a similar form of elasticity that tolerates variations in the delays or the latencies of the computation and communication resources of a system. This flexibility comes ... -
Petri net analysis using boolean manipulation
(Springer, 1994)
Capítol de llibre
Accés obertThis paper presents a novel analysis approach for bounded Petri nets. The net behavior is modeled by boolean functions, thus reducing reasoning about Petri nets to boolean calculation. The state explosion problem is managed ... -
Petrify: a tool for manipulating concurrent specifications and synthesis of asynchronous controllers
(1997-03)
Article
Accés obertPetrify is a tool for (1) manipulating concurrent specifications and (2) synthesis and optimization of asynchronous control circuits. Given a Petri Net (PN), a Signal Transition Graph (STG), or a Transition System (TS) it ... -
Petrify: a tool for manipulating concurrent specifications and synthesis of asynchronous controllers
(Universitat Politècnica de Catalunya (UPC), 1996)
Text en actes de congrés
Accés obertPetrifyis a tool for (1) manipulating concurrent specifications and (2) synthesis and optimization of asynchronous control circuits. Given a Petri Net (PN), a Signal Transition Graph (STG), or a Transition ... -
Physical planning for the architectural exploration of large-scale chip multiprocessors
(2013)
Comunicació de congrés
Accés restringit per política de l'editorialThis paper presents an integrated flow for architectural exploration and physical planning of large-scale hierarchical tiled CMPs. Classical floorplanning and wire planning techniques have been adapted to incorporate layout ... -
Physical-aware link allocation and route assignment for chip multiprocessing
(Institute of Electrical and Electronics Engineers (IEEE), 2010)
Text en actes de congrés
Accés obertThe architecture definition, design, and validation of the interconnect networks is a key step in the design of modern on-chip systems. This paper proposes a mathematical formulation of the problem of simultaneously defining ... -
Physical-aware system-level design for tiled hierarchical chip multiprocessors
(ACM Press. Association for Computing Machinery, 2013)
Text en actes de congrés
Accés obertTiled hierarchical architectures for Chip Multiprocessors (CMPs) represent a rapid way of building scalable and power-e fficient many-core computing systems. At the early stages of the design of a CMP, physical parameters ... -
Polynomial algorithms for the synthesis of hazard-free circuits from signal transition graphs
(Institute of Electrical and Electronics Engineers (IEEE), 1993)
Text en actes de congrés
Accés obertMethods for the synthesis of asynchronous circuits from signal transition graphs (STGs) have commonly used the state graph to solve the two main steps of this process: the state assignment problem and the generation of ... -
Power-optimal mapping of CNN applications to cloud-based Multi-FPGA platforms
(2020-12)
Article
Accés obertMulti-FPGA platforms like Amazon Web Services F1 are perfect to accelerate multi-kernel pipelined applications, like Convolutional Neural Networks (CNNs). To reduce energy consumption, we propose to upload at runtime the ... -
Process discovery algorithms using numerical abstract domains
(2014-12-01)
Article
Accés obertThe discovery of process models from event logs has emerged as one of the crucial problems for enabling the continuous support in the life-cycle of an information system. However, in a decade of process discovery research, ... -
Process mining meets abstract interpretation
(2010-07)
Report de recerca
Accés obertThe discovery of process models out of system traces is an interesting problem that has received significant attention in the last years. In this work, a theory for the derivation of a Petri net from a set of traces is ... -
Process windows
(Institute of Electrical and Electronics Engineers (IEEE), 2017)
Text en actes de congrés
Accés obertWe describe a method for formally representing the behaviour of complex processes by process windows. Each window covers a part of the system behaviour, i.e. a part of the underlying transition system, and is easier to ... -
Programación VLSI y síntesis de circuitos asíncronos mediante composición de redes de Petri
(1995)
Text en actes de congrés
Accés obertTangram es un lenguaje de programación VLSI traducible automáticamente a redes de módulos asíncronos llamados componentes de sincronización. En este artículo se usan los Grafos de Transiciones de Señales (STGs) para describir ...
