Ara es mostren els items 12-18 de 18

    • Niveles de competencia de los objetivos formativos en las ingenierías 

      Valero García, Miguel; Navarro Guerrero, Juan José (2001)
      Text en actes de congrés
      Accés obert
      En este artículo se discute la cuestión del nivel de competencia de los objetivos formativos en nuestras materias, y las implicaciones en los métodos docentes y de evaluación. A partir de esta discusión se ofrecen ...
    • Partitioning: an essential step in mapping algorithms into systolic array processors 

      Navarro Guerrero, Juan José; Llaberia Griñó, José M.; Valero Cortés, Mateo (1987-07)
      Article
      Accés obert
      The efficient solution of a large problem on a small systolic array requires good partitioning techniques to split the problem into subproblems that fit the array size.
    • Reusing cached schedules in an out-of-order processor with in-order issue logic 

      Palomar Pérez, Óscar; Juan, Toni; Navarro Guerrero, Juan José (2009)
      Text en actes de congrés
      Accés obert
      The complex and powerful out-of-order issue logic dismisses the repetitive nature of the code, unlike what caches or branch predictors do. We show that 90% of the cycles, the group of instructions selected by the issue ...
    • Solving matrix problems with no size restriction on a systolic array processor 

      Navarro Guerrero, Juan José; Llaberia Griñó, José M.; Valero Cortés, Mateo (1986)
      Report de recerca
      Accés obert
      In this paper we propose several data structures partitioning and transformation schemes, in order to get an efficient execution of various matrix algorithms without any size resriction. The following matrix operations are ...
    • Systematic design of two level pipelined systolic arrays with data contraflow 

      Valero García, Miguel; Navarro Guerrero, Juan José; Llaberia Griñó, José M.; Valero Cortés, Mateo (1988)
      Text en actes de congrés
      Accés obert
      Many systolic algorithms and related design methodologies have been recently proposed. Frecuently, in these systolic algorithms practical considerations are not taken into account. Equitatively distributed load between ...
    • Systolic implementation for deconvolution iterative algorithm 

      Navarro Guerrero, Juan José; Casares Giner, Vicente (1985)
      Report de recerca
      Accés obert
      Systolic architectures implement regular algorithms in hardware, in order to obtain high computational throughput. In this paper we provide a modular architecture for a deconvolution iterative algorithm. The basic module ...
    • Transformation of systolic algorithms for interleaving partitions 

      Fernández Jiménez, Agustín; Llaberia Griñó, José M.; Navarro Guerrero, Juan José; Valero García, Miguel (1990)
      Text en actes de congrés
      Accés obert
      A systematic method to map systolizable problems onto multicomputers is presented in this paper. A systolizable problem is a problem for which it is possible to design a Systolic Algorithm. This method selects and transforms ...