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    • VALib and SimpleVector: Tools for rapid initial research on vector architectures 

      Stanic, Milan; Palomar Pérez, Óscar; Ratkovic, Ivan; Duric, Milovan; Unsal, Osman Sabri; Cristal Kestelman, Adrián; Valero Cortés, Mateo (Association for Computing Machinery (ACM), 2014)
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      Vector architectures have been traditionally applied to the supercomputing domain with many successful incarnations. The energy efficiency and high performance of vector processors, as well as their applicability in other ...

    • Vector extensions for decision support DBMS acceleration 

      Hayes, Timothy; Palomar Pérez, Óscar; Unsal, Osman Sabri; Cristal Kestelman, Adrián; Valero Cortés, Mateo (IEEE, 2012)
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      Database management systems (DBMS) have become an essential tool for industry and research and are often a significant component of data centres. As a result of this criticality, efficient execution of DBMS engines has ...

    • Vector processing-aware advanced clock-gating techniques for low-power fused multiply-add 

      Ratkovic, Ivan; Palomar Pérez, Óscar; Stanic, Milan; Unsal, Osman Sabri; Cristal Kestelman, Adrián; Valero Cortés, Mateo (2018-04-04)
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      The need for power efficiency is driving a rethink of design decisions in processor architectures. While vector processors succeeded in the high-performance market in the past, they need a retailoring for the mobile market ...

    • VIA: A smart scratchpad for vector units with application to sparse matrix computations 

      Pavón Rivera, Julián; Vargas Valdivieso, Iván; Barredo Ferreira, Adrián; Marimon Illana, Joan; Moretó Planas, Miquel; Moll Echeto, Francisco de Borja; Unsal, Osman Sabri; Valero Cortés, Mateo; Cristal Kestelman, Adrián (Institute of Electrical and Electronics Engineers (IEEE), 2021)
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      Sparse matrix operations are critical kernels in multiple application domains such as High Performance Computing, artificial intelligence and big data. Vector processing is widely used to improve performance on mathematical ...

    • Virtual registers 

      González Colás, Antonio María; Valero Cortés, Mateo; González González, José; Monreal Arnal, Teresa (Institute of Electrical and Electronics Engineers (IEEE), 1997)
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      The number of physical registers is one of the critical issues of current superscalar out-of-order processors. Conventional architectures allocate, in the decoding stage, a new storage location (e.g. a physical register) ...

    • Virtual-physical registers 

      González Colás, Antonio María; González González, José; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 1998)
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      A novel dynamic register renaming approach is proposed in this work. The key idea of the novel scheme is to delay the allocation of physical registers until a late stage in the pipeline, instead of doing it in the decode ...

    • Vitruvius+: An area-efficient RISC-V decoupled vector coprocessor for high performance computing applications 

      Minervini Minervini, Francesco; Palomar Pérez, Óscar; Unsal, Osman Sabri; Reggiani, Enrico; Quiroga Esparza, Josué Vladimir; Marimon Illana, Joan; Rojas Morales, Carlos; Figueras Bagué, Roger; Ruíz Ramírez, Abraham Josafat; González Trejo, Alberto; Mendoza Escobar, Jonnatan; Vargas Valdivieso, Ivan; Hernández Calderón, César Alejandro; Cabre Olive, Joan; Khoirunisya, Lina; Bouhali, Mustapha; Pavón Rivera, Julián; Moll Echeto, Francisco de Borja; Olivieri, Mauro; Kovac, Mario; Kovac, Mate; Dragic, Leon; Valero Cortés, Mateo; Cristal Kestelman, Adrián (2023-03-01)
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      The maturity level of RISC-V and the availability of domain-specific instruction set extensions, like vector processing, make RISC-V a good candidate for supporting the integration of specialized hardware in processor cores ...

    • VSR sort: a novel vectorised sorting algorithm and architecture extensions for future microprocessors 

      Hayes, Timothy; Palomar Pérez, Óscar; Unsal, Osman Sabri; Cristal Kestelman, Adrián; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2015)
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      Sorting is a widely studied problem in computer science and an elementary building block in many of its subfields. There are several known techniques to vectorise and accelerate a handful of sorting algorithms by using ...

    • Widening resources: a cost-effective technique for aggressive ILP architectures 

      López Álvarez, David; Llosa Espuny, José Francisco; Valero Cortés, Mateo; Ayguadé Parra, Eduard (Institute of Electrical and Electronics Engineers (IEEE), 1998)
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      The inherent instruction-level parallelism (ILP) of current applications (specially those based on floating point computations) has driven hardware designers and compilers writers to investigate aggressive techniques for ...

    • WormBench: technical report 

      Zyulkyarov, Ferad Hasanov; Cvijic, Sanja; Unsal, Osman Sabri; Cristal Kestelman, Adrián; Ayguadé Parra, Eduard; Harris, Tim; Valero Cortés, Mateo (2008-08)
      Report de recerca
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      Transactional Memory (TM) is a promising new technology that makes it possible to ease writing multi-threaded applications. Many different TM implementations exist, unfortunately most of those TM systems are currently ...