Exploració per autor "Valero Cortés, Mateo"
Ara es mostren els items 226-245 de 357
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PAMS: pattern aware memory system for embedded systems
(Institute of Electrical and Electronics Engineers (IEEE), 2015)
Text en actes de congrés
Accés obertIn this paper, we propose a hardware mechanism for embedded multi-core memory system called Pattern Aware Memory System (PAMS). The PAMS supports static and dynamic data structures using descriptors and specialized memory ... -
Parallel processing in biological sequence comparison using general purpose processors
(Institute of Electrical and Electronics Engineers (IEEE), 2005)
Text en actes de congrés
Accés obertThe comparison and alignment of DNA and protein sequences are important tasks in molecular biology and bioinformatics. One of the most well known algorithms to perform the string-matching operation present in these tasks ... -
PARSECSs: Evaluating the impact of task parallelism in the PARSEC benchmark suite
(2015-12-01)
Article
Accés obertIn this work, we show how parallel applications can be implemented efficiently using task parallelism. We also evaluate the benefits of such parallel paradigm with respect to other approaches. We use the PARSEC benchmark ... -
Partitioning: an essential step in mapping algorithms into systolic array processors
(1987-07)
Article
Accés obertThe efficient solution of a large problem on a small systolic array requires good partitioning techniques to split the problem into subproblems that fit the array size. -
Per-task energy accounting in computing systems
(2013)
Report de recerca
Accés obertWe present for the first time the concept of per-task energy accounting (PTEA) and relate it to per-task energy metering (PTEM). We show the benefits of supporting both in future computing systems. Using the shared last-level ... -
Per-task energy metering and accounting in the multicore era
(Barcelona Supercomputing Center, 2015-05-05)
Text en actes de congrés
Accés obertEnergy has become arguably the most expensive resource in a computing system. As multi-core processors are the preferred processing platform across different computing domains, measuring the energy usage draws vast attention. ... -
Performance analysis of a hardware accelerator of dependence management for taskbased dataflow programming models
(Institute of Electrical and Electronics Engineers (IEEE), 2016)
Text en actes de congrés
Accés obertAlong with the popularity of multicore and manycore, task-based dataflow programming models obtain great attention for being able to extract high parallelism from applications without exposing the complexity to programmers. ... -
Performance analysis of a new packet trace compressor based on TCP flow clustering
(Institute of Electrical and Electronics Engineers (IEEE), 2005)
Text en actes de congrés
Accés obertIn this paper we study the properties of a new packet trace compression method based on clustering of TCP flows. With our proposed method, the compression ratio that we achieve is around 3%, reducing the file size, for ... -
Performance analysis of sequence alignment applications
(Institute of Electrical and Electronics Engineers (IEEE), 2006)
Text en actes de congrés
Accés obertAdvances in molecular biology have led to a continued growth in the biological information generated by the scientific community. Additionally, this area has become a multi-disciplinary field, including components of ... -
Performance and energy effects on task-based parallelized applications: User-directed versus manual vectorization
(2018-06)
Article
Accés obertHeterogeneity, parallelization and vectorization are key techniques to improve the performance and energy efficiency of modern computing systems. However, programming and maintaining code for these architectures poses a ... -
Performance and power evaluation of clustered VLIW processors with wide functional units
(2004-11)
Article
Accés restringit per política de l'editorialArchitectural resources and program recurrences are themain limitations to the amount of Instruction-Level Parallelism (ILP) exploitable from loops. To increase the number of operations per second, current designs use high ... -
Performance evaluation of macroblock-level parallelization of H.264 decoding on a cc-NUMA multiprocessor architecture
(2009-04-23)
Text en actes de congrés
Accés restringit per política de l'editorialThis paper presents a study of the performance scalability of a macroblock-level parallelization of the H.264 decoder for High De nition (HD) applications on a multiprocessor architecture. We have implemented this ... -
Performance evaluation of macroblock-level parallelization of H.264 decoding on a cc-NUMA multiprocessor architecture
(2009-06)
Article
Accés restringit per política de l'editorialEste artículo presenta un estudio de la escalabilidad del rendimiento en el paralelismo a nivel macro bloque de un decodificador H.264 para aplicaciones de alta definición (HD) en arquitecturas de múltiples procesadores. ... -
Performance impact of the interconnection network on MareNostrum applications
(-, 2007)
Text en actes de congrés
Accés obertInterconnection networks are one of the fundamental components of a supercomputing facility, and one of the most expensive parts. They represent one of the main differences between two supercomputers built from the same ... -
Performance impact of unaligned memory operations in SIMD extensions for video CODEC applications
(Institute of Electrical and Electronics Engineers (IEEE), 2007)
Text en actes de congrés
Accés obertAlthough SIMD extensions are a cost effective way to exploit the data level parallelism present in most media applications, we will show that they had have a very limited memory architecture with a weak support for unaligned ... -
Performance power efficiency and scalabity of asymmetric chip multiprocessors
(2006-01)
Article
Accés restringit per política de l'editorialThis paper evaluates asymmetric cluster chip multiprocessor (ACCMP) architectures as a mechanism to achieve the highest performance for a given power budget. ACCMPs execute serial phases of multithreaded programs on large ... -
Physical vs. physically-aware estimation flow: case study of design space exploration of adders
(Institute of Electrical and Electronics Engineers (IEEE), 2014)
Text en actes de congrés
Accés restringit per política de l'editorialSelecting an appropriate estimation method for a given technology and design is of crucial interest as the estimations guide future project and design decisions. The accuracy of the estimations of area, timing, and power ... -
Picos, a hardware task-dependence manager for task-based dataflow programming models
(Institute of Electrical and Electronics Engineers (IEEE), 2017)
Text en actes de congrés
Accés obertTask-based programming Task-based programming models such as OpenMP, Intel TBB and OmpSs are widely used to extract high level of parallelism of applications executed on multi-core and manycore platforms. These programming ... -
Picos: A hardware runtime architecture support for OmpSs
(Elsevier, 2015-12)
Article
Accés obertOmpSs is a programming model that provides a simple and powerful way of annotating sequential programs to exploit heterogeneity and task parallelism based on runtime data dependency analysis, dataflow scheduling and ... -
POSTER: an integrated vector-scalar design on an in-order ARM core
(Association for Computing Machinery (ACM), 2016)
Text en actes de congrés
Accés restringit per política de l'editorialIn the low-end mobile processor market, power, energy and area budgets are significantly lower than in other markets (e.g. servers or high-end mobile markets). It has been shown that vector processors are a highly ...
