Exploració per autor "Valero Cortés, Mateo"
Ara es mostren els items 177-196 de 357
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Late allocation and early release of physical registers
(2004-10)
Article
Accés obertThe register file is one of the critical components of current processors in terms of access time and power consumption. Among other things, the potential to exploit instruction-level parallelism is closely related to the ... -
Latency tolerant branch predictors
(IEEE Press, 2003)
Text en actes de congrés
Accés obertThe access latency of branch predictors is a well known problem of fetch engine design. Prediction overriding techniques are commonly accepted to overcome this problem. However, prediction overriding requires a complex ... -
Lifetime-sensitive modulo scheduling in a production environment
(2001-03)
Article
Accés obertThis paper presents a novel software pipelining approach, which is called Swing Modulo Scheduling (SMS). It generates schedules that are near optimal in terms of initiation interval, register requirements, and stage count. ... -
Long DNA sequence comparison on multicore architectures
(Springer Verlag, 2010)
Text en actes de congrés
Accés restringit per política de l'editorialBiological sequence comparison is one of the most important tasks in Bioinformatics. Due to the growth of biological databases, sequence comparison is becoming an important challenge for high performance computing, especially ... -
Loop parallelization: revisiting framework of unimodular transformations
(Institute of Electrical and Electronics Engineers (IEEE), 1996)
Text en actes de congrés
Accés obertThe paper extends the framework of linear loop transformations adding a new nonlinear step at the transformation process. The current framework of linear loop transformation cannot identify a significant fraction of ... -
Machine learning performance prediction model for heterogeneous systems
(Barcelona Supercomputing Center, 2017-05-04)
Text en actes de congrés
Accés obert -
MAPC: memory access pattern based controller
(Institute of Electrical and Electronics Engineers (IEEE), 2014)
Text en actes de congrés
Accés restringit per política de l'editorialTraditionally, system designers have attempted to improve system performance by scheduling the processing cores and by exploring different memory system configurations and there is comparatively less work done scheduling ... -
MAPC: memory access pattern based controller
(Institute of Electrical and Electronics Engineers (IEEE), 2014)
Text en actes de congrés
Accés restringit per política de l'editorialTraditionally, system designers have attempted to improve system performance by scheduling the processing cores and by exploring different memory system configurations and there is comparatively less work done scheduling ... -
Mathematical models to evaluate the memory interference in multimicrocomputer systems
(Universidad Nacional Autónoma de México, 1981)
Text en actes de congrés
Accés obertIn the last decade we have witnessed great advances in the integrated circuits technology. Those advances make it possible nowadays for the manufacturing, at reasonable prices of MOS technology memories that are faster ... -
Mathematical representation of the Hardware Round-Robin Scheduler analytical model for single-ISA heterogeneous architectures
(Barcelona Supercomputing Center, 2015-05-05)
Text en actes de congrés
Accés obert -
Maximizing multithreaded multicore architectures through thread migrations
(2009)
Report de recerca
Accés obertHeterogeneity in general-purpose workloads often end up in non optimal per-thread hardware resource usage. The current trend towards multicore architectures, containing several multithreaded cores, increases the need of a ... -
Measuring operating system overhead on CMT processors
(IEEE Computer Society Publications, 2008)
Text en actes de congrés
Accés obertNumerous studies have shown that Operating System (OS) noise is one of the reasons for significant performance degradation in clustered architectures. Although many studies examine the OS noise for High Performance Computing ... -
Measuring operating system overhead on Sun UltraSparc T1 processor
(2009-06)
Text en actes de congrés
Accés obertNumerous studies have shown that Operating System (OS) noise is one of the reasons for significant performance degradation in clustered architectures. Although many studies examine the OS noise for High Performance Computing, ... -
MFLUSH: handling long-latency loads in SMT on-chip multiprocessors
(IEEE Computer Society Publications, 2008)
Text en actes de congrés
Accés obertNowadays, there is a clear trend in industry towards employing the growing amount of transistors on chip in replicating execution cores (CMP), where each core is Simultaneous Multithreading (SMT). State-of-the-art ... -
Microarchitectural support for speculative register renaming
(Institute of Electrical and Electronics Engineers (IEEE), 2007)
Text en actes de congrés
Accés obertThis paper proposes and evaluates a new microarchitecture for out-of-order processors that supports speculative renaming. We call speculative renaming to the speculative omission of physical register allocation along with ... -
Mirs: modulo scheduling with integrated register spilling
(2003-01)
Article
Accés restringit per política de l'editorialThe overlapping of loop iterations in software pipelining techniques imposes high register requirements. The schedule for a loop is valid if it requires at most the number of registers available in the target architecture. ... -
MLP-aware dynamic cache partitioning
(Institute of Electrical and Electronics Engineers (IEEE), 2007)
Comunicació de congrés
Accés obertThe limitation imposed by instruction-level parallelism (ILP) has motivated the use of thread-level parallelism (TLP) as a common strategy for improving processor performance. TLP paradigms such as simultaneous multithreading ... -
Modulo scheduling with integrated register spilling for clustered VLIW architectures
(Institute of Electrical and Electronics Engineers (IEEE), 2001)
Text en actes de congrés
Accés obertClustering is a technique to decentralize the design of future wide issue VLIW cores and enable them to meet the technology constraints in terms of cycle time, area and power dissipation. In a clustered design, registers ... -
Modulo scheduling with reduced register pressure
(1998-06)
Article
Accés obertSoftware pipelining is a scheduling technique that is used by some product compilers in order to expose more instruction level parallelism out of innermost loops. Module scheduling refers to a class of algorithms for ... -
MOM: a matrix SIMD instruction set architecture for multimedia applications
(Institute of Electrical and Electronics Engineers (IEEE), 1999)
Text en actes de congrés
Accés obertMOM is a novel matrix-oriented ISA paradigm for multimedia applications, based on fusing conventional vector ISAs with SIMD ISAs such as MMX. This paper justifies why MOM is a suitable alternative for the multimedia domain ...
