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    • FAME: FAirly MEasuring multithreaded architectures 

      Vera, Javier; Cazorla, Francisco; Pajuelo González, Manuel Alejandro; Santana Jaria, Oliverio J.; Fernandez Garcia, Enrique; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2007)
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      Nowadays, multithreaded architectures are becoming more and more popular. In order to evaluate their behavior, several methodologies and metrics have been proposed. A methodology defines when the measurements of a given ...

    • Fast speculative address generation and way caching for reducing L1 data cache energy 

      Nicolaescu, Dan; Salamat, Babak; Veidenbaum, Alex; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2006)
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      L1 data caches in high-performance processors continue to grow in set associativity. Higher associativity can significantly increase the cache energy consumption. Cache access latency can be affected as well, leading to ...

    • FaulTM: Fault-tolerance using hardware transactional memory 

      Yalcin, Gulay; Unsal, Osman Sabri; Hur, Ibrahim; Cristal Kestelman, Adrián; Valero Cortés, Mateo (2010)
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      Fault-tolerance has become an essential concern for processor designers due to increasing soft-error rates. In this study, we are motivated by the fact that Transactional Memory (TM) hardware provides an ideal base upon ...

    • Fetching instruction streams 

      Ramírez Bellido, Alejandro; Santana Jaria, Oliverio J.; Larriba Pey, Josep; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2002)
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      Fetch performance is a very important factor because it effectively limits the overall processor performance. However there is little performance advantage in increasing front-end performance beyond what the back-end can ...

    • FIMSIM: A fault injection infrastructure for microarchitectural simulators 

      Yalcin, Gulay; Unsal, Osman Sabri; Cristal Kestelman, Adrián; Valero Cortés, Mateo (2011)
      Report de recerca
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      Fault injection is a widely used approach for experiment-based dependability evaluation in which faults can be injected to the hardware, to the simulator or to the software. Simulation based fault injection is more appealing ...

    • FlexVC: Flexible virtual channel management in low-diameter networks 

      Fuentes, Pablo; Vallejo, Enrique; Beivide Palacio, Ramon; Minkenberg, Cyriel; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2017)
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      Deadlock avoidance mechanisms for lossless lowdistance networks typically increase the order of virtual channel (VC) index with each hop. This restricts the number of buffer resources depending on the routing mechanism and ...

    • Fog function virtualization: A flexible solution for IoT applications 

      Roca, Damian; Quiroga, Josue V.; Valero Cortés, Mateo; Nemirovsky, Mario (Institute of Electrical and Electronics Engineers (IEEE), 2017)
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      The Internet of Things applications must carefully assess certain crucial factors such as the real-time and largely distributed nature of the “things”. Fog Computing provides an architecture to satisfy those requirements ...

    • From plasma to beefarm: Design experience of an FPGA-based multicore prototype 

      Sonmez, Nehir; Arcas Abella, Oriol; Sayilar, Gokhan; Unsal, Osman Sabri; Cristal Kestelman, Adrián; Hur, Ibrahim; Singh, Satnam; Valero Cortés, Mateo (Springer, 2011)
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      In this paper, we take a MIPS-based open-source uniprocessor soft core, Plasma, and extend it to obtain the Beefarm infrastructure for FPGA-based multiprocessor emulation, a popular research topic of the last few years ...

    • Future vector microprocessor extensions for data aggregations 

      Hayes, Timothy; Palomar, Oscar; Unsal, Osman Sabri; Cristal Kestelman, Adrián; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2016)
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      As the rate of annual data generation grows exponentially, there is a demand to aggregate and summarise vast amounts of information quickly. In the past, frequency scaling was relied upon to push application throughput. ...

    • Fuzzy memoization for floating-point multimedia applications 

      Álvarez Martínez, Carlos; Corbal San Adrián, Jesús; Valero Cortés, Mateo (2005-07)
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      Instruction memoization is a promising technique to reduce the power consumption and increase the performance of future low-end/mobile multimedia systems. Power and performance efficiency can be improved by reusing instances ...

    • General purpose task-dependence management hardware for task-based dataflow programming models 

      Tan, Xubin; Bosch, Jaume; Vidal, Miquel; Alvarez, Carlos; Jimenez-Gonzalez, Daniel; Ayguadé Parra, Eduard; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2017)
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      Task-based programming models such as OpenMP, IntelTBB and OmpSs offer the possibility of expressing dependences among tasks to drive their execution at runtime. Managing these dependences introduces noticeable overheads ...

    • Generating a periodic pattern for VLIW 

      Barrado Muxí, Cristina; Labarta Mancho, Jesús José; Ayguadé Parra, Eduard; Valero Cortés, Mateo (Universidad de Málaga, 1995)
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      Fine-grain parallelism available in VLIW and superscalar processors can be mainly exploited in computational intensive loops. Aggressive scheduling techniques are required to fully exploit this parallelism. In this paper ...

    • Global misrouting policies in two-level hierarchical networks 

      Garcia, Marina; Vallejo, Enrique; Beivide Palacio, Julio Ramón; Odriozola, Miguel; Camarero Coterillo, Cristobal; Valero Cortés, Mateo; Labarta Mancho, Jesús José; Rodríguez, Germán (2013)
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      Dragonfly networks are composed of interconnected groups of routers. Adaptive routing allows packets to be forwarded minimally or non-minimally adapting to the traffic conditions in the network. While minimal routing sends ...

    • GMT: Enabling easy development and efficient execution of irregular applications on commodity clusters 

      Morari, Alessandro; Villa, Oreste; Tumeo, Antonino; Chavarria Miranda, Daniel; Valero Cortés, Mateo (Association for Computing Machinery (ACM), 2013)
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      In this poster we introduce GMT (Global Memory and Threading library), a custom runtime library that enables efficient execution of irregular applications on commodity clusters. GMT only requires a cluster with x86 nodes ...

    • Graph partitioning applied to DAG scheduling to reduce NUMA effects 

      Sánchez Barrera, Isaac; Casas, Marc; Moretó Planas, Miquel; Ayguadé Parra, Eduard; Labarta Mancho, Jesús José; Valero Cortés, Mateo (Association for Computing Machinery (ACM), 2018)
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      The complexity of shared memory systems is becoming more relevant as the number of memory domains increases, with different access latencies and bandwidth rates depending on the proximity between the cores and the devices ...

    • Hardware scheduling algorithms for asymmetric single-ISA CMPs 

      Markovic, Nikola; Nemirovsky, Daniel; Unsal, Osman Sabri; Valero Cortés, Mateo; Cristal Kestelman, Adrián (Barcelona Supercomputing Center, 2015-05-05)
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      As thread level parallelism in applications has continued to expand, so has research in chip multi-core processors. Since more and more applications become multi-threaded we expect to find a growing number of threads ...

    • Hardware schemes for early register release 

      Monreal Arnal, Teresa; Viñals Yufera, Víctor; González Colás, Antonio María; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2002)
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      Register files are becoming one of the critical components of current out-of-order processors in terms of delay and power consumption, since their potential to exploit instruction-level parallelism is quite related to the ...

    • Hardware transactional memory with software-defined conflicts 

      Titos Gil, Rubén; Acacio, Manuel E.; García, José M.; Harris, Tim; Cristal Kestelman, Adrián; Unsal, Osman Sabri; Hur, Ibrahim; Valero Cortés, Mateo (2010)
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      In this paper we propose conflict-defined blocks, a programming language construct that allows programmers to change the concept of conflict from one transaction to another, or even throughout the course of the same ...

    • HD-VideoBench: A benchmark for evaluating high definition digital video applications 

      Álvarez Mesa, Mauricio; Salamí San Juan, Esther; Ramírez Bellido, Alejandro; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2007)
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      HD-VideoBench is a benchmark devoted to high definition (HD) digital video processing. It includes a set of video encoders and decoders (Codecs) for the MPEG-2, MPEG-4 and H.264 video standards. The applications were ...

    • Heuristics for register-constrained software pipelining 

      Llosa Espuny, José Francisco; Valero Cortés, Mateo; Ayguadé Parra, Eduard (Institute of Electrical and Electronics Engineers (IEEE), 1996)
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      Software Pipelining is a loop scheduling technique that extracts parallelism from loops by overlapping the execution of several consecutive iterations. There has been a significant effort to produce throughput-optimal ...