Ara es mostren els items 104-123 de 357

    • Early 21st Century processors 

      Vajapeyam, Sriram; Valero Cortés, Mateo (2001-04)
      Article
      Accés obert
      The computer architecture arena faces exciting challenges as it attempts to meet the design goals and constraints that new markets, changing applications and fast-moving semiconductor technology impose.
    • EcoTM: Conflict-aware economical unbounded hardware transactional memory 

      Tomić, Saša; Akpinar, Ege; Cristal Kestelman, Adrián; Unsal, Osman Sabri; Valero Cortés, Mateo (Elsevier, 2013)
      Text en actes de congrés
      Accés obert
      Transactional Memory (TM) is a promising paradigm for parallel programming. TM allows a thread to make a series of memory accesses as a single, atomic, transaction, while avoiding deadlocks, livelocks, and other problems ...
    • Effective instruction prefetching via fetch prestaging 

      Falcón Samper, Ayose Jesús; Ramírez Bellido, Alejandro; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2005)
      Text en actes de congrés
      Accés obert
      As technological process shrinks and clock rate increases, instruction caches can no longer be accessed in one cycle. Alternatives are implementing smaller caches (with higher miss rate) or large caches with a pipelined ...
    • Effective usage of vector registers in advanced vector architectures 

      Villa, Luis; Espasa Sans, Roger; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 1997)
      Text en actes de congrés
      Accés obert
      This paper presents data confirming the fact that traditional vector architectures can not reduce their vector register length without suffering a severe performance penalty. However, we will show that by combining the ...
    • Effective usage of vector registers in decoupled vector architectures 

      Villa, Luis; Espasa Sans, Roger; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 1998)
      Text en actes de congrés
      Accés obert
      The paper presents a study of the impact of reducing the vector register size in a decoupled vector architecture. In traditional in-order vector architectures long vector registers have typically been the norm. The authors ...
    • Efficiency analysis of modern vector architectures: vector ALU sizes, core counts and clock frequencies 

      Barredo Ferreira, Adrián; Cebrián González, Juan Manuel; Valero Cortés, Mateo; Casas, Marc; Moretó Planas, Miquel (2020-03)
      Article
      Accés obert
      Moore’s Law predicted that the number of transistors on a chip would double approximately every 2 years. However, this trend is arriving at an impasse. Optimizing the usage of the available transistors within the thermal ...
    • Efficient cache architectures for reliable hybrid voltage operation using EDC codes 

      Maric, Bojan; Abella Ferrer, Jaume; Valero Cortés, Mateo (2013)
      Text en actes de congrés
      Accés obert
      Semiconductor technology evolution enables the design of sensor-based battery-powered ultra-low-cost chips (e.g., below 1 p) required for new market segments such as body, urban life and environment monitoring. Caches have ...
    • Efficient routing mechanisms for Dragonfly networks 

      García, Marina; Vallejo, Enrique; Beivide Palacio, Julio Ramón; Odriozola, Miguel; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2013)
      Comunicació de congrés
      Accés obert
      High-radix hierarchical networks are cost-effective topologies for large scale computers. In such networks, routers are organized in super nodes, with local and global interconnections. These networks, known as Dragonflies, ...
    • Emergent behaviors in the Internet of things: The ultimate ultra-large-scale system 

      Roca, Damian; Nemirovsky, Daniel; Nemirovsky, Mario; Milito, Rodolfo; Valero Cortés, Mateo (2016-11)
      Article
      Accés obert
      To reach its potential, the Internet of Things (IoT) must break down the silos that limit applications' interoperability and hinder their manageability. Doing so leads to the building of ultra-large-scale systems (ULSS) ...
    • Enabling preemptive multiprogramming on GPUs 

      Tanasic, Ivan; Gelado Fernandez, Isaac; Cabezas, Javier; Ramírez Bellido, Alejandro; Navarro, Nacho; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2014)
      Text en actes de congrés
      Accés obert
      GPUs are being increasingly adopted as compute accelerators in many domains, spanning environments from mobile systems to cloud computing. These systems are usually running multiple applications, from one or several users. ...
    • Enabling SMT for real-time embedded systems 

      Cazorla Almeida, Francisco Javier; Knijnenburg, Peter M.W.; Sakellariou, Rizos; Fernandez Prieto, Enrique; Ramírez Bellido, Alejandro; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2004)
      Text en actes de congrés
      Accés obert
      In order to deal with real time constraints, current embedded processors are usually simple in-order processors with no speculation capabilities to ensure that execution times of applications are predictable. However, ...
    • Enlarging instruction streams 

      Santana Jaria, Oliverio J.; Ramírez Bellido, Alejandro; Valero Cortés, Mateo (2007-10)
      Article
      Accés obert
      The stream fetch engine is a high-performance fetch architecture based on the concept of an instruction stream. We call a sequence of instructions from the target of a taken branch to the next taken branch, potentially ...
    • Evaluating the impact of OpenMP 4.0 extensions on relevant parallel workloads 

      Vidal Ortiz, Raul; Casas, Marc; Moretó Planas, Miquel; Chasapis, Dimitrios; Ferrer Ibáñez, Roger; Martorell Bofill, Xavier; Ayguadé Parra, Eduard; Labarta Mancho, Jesús José; Valero Cortés, Mateo (Springer, 2015)
      Text en actes de congrés
      Accés obert
      OpenMP has been for many years the most widely used programming model for shared memory architectures. Periodically, new features are proposed and some of them are finally selected for inclusion in the OpenMP standard. The ...
    • Evaluation of vectorization potential of Graph500 on Intel's Xeon Phi 

      Stanic, Milan; Palomar Pérez, Óscar; Ratkovic, Ivan; Duric, Milovan; Unsal, Osman Sabri; Cristal Kestelman, Adrián; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2014)
      Text en actes de congrés
      Accés obert
      Graph500 is a data intensive application for high performance computing and it is an increasingly important workload because graphs are a core part of most analytic applications. So far there is no work that examines if ...
    • Evolutionary system for prediction and optimization of hardware architecture performance 

      Castillo, Pedro Angel; Merelo, Juan Julián; Moretó Planas, Miquel; Cazorla Almeida, Francisco Javier; Valero Cortés, Mateo; Mora, Antonio; Laredo, Juan Luís; McKee, Sally (2008-06)
      Text en actes de congrés
      Accés obert
      The design of computer architectures is a very complex problem. The multiple parameters make the number of possible combinations extremely high. Many researchers have used simulation, although it is a slow solution since ...
    • EVX: vector execution on low power EDGE cores 

      Duric, Milovan; Palomar Pérez, Óscar; Smith, Aaron; Unsal, Osman Sabri; Cristal Kestelman, Adrián; Valero Cortés, Mateo; Burger, Doug (European Interactive Digital Advertising Alliance (EDAA), 2014)
      Text en actes de congrés
      Accés restringit per política de l'editorial
      In this paper, we present a vector execution model that provides the advantages of vector processors on low power, general purpose cores, with limited additional hardware. While accelerating data-level parallel (DLP) ...
    • Explaining dynamic cache partitioning speed ups 

      Moretó Planas, Miquel; Cazorla, Francisco; Ramírez Bellido, Alejandro; Valero Cortés, Mateo (2007-01)
      Article
      Accés obert
      Cache partitioning has been proposed as an interesting alternative to traditional eviction policies of shared cache levels in modern CMP architectures: throughput is improved at the expense of a reasonable cost. However, ...
    • Exploiting a new level of DLP in multimedia applications 

      Corbal San Adrián, Jesús; Valero Cortés, Mateo; Espasa Sans, Roger (Institute of Electrical and Electronics Engineers (IEEE), 1999)
      Text en actes de congrés
      Accés obert
      This paper proposes and evaluates MOM: a novel ISA paradigm targeted at multimedia applications. By fusing conventional vector ISA approaches together with more recent SIMD-like (Single Instruction Multiple Data) ISAs (such ...
    • Exploiting asynchrony from exact forward recovery for DUE in iterative solvers 

      Jaulmes, Luc; Casas, Marc; Moretó Planas, Miquel; Ayguadé Parra, Eduard; Labarta Mancho, Jesús José; Valero Cortés, Mateo (2015)
      Report de recerca
      Accés obert
      This paper presents a method to protect iterative solvers from Detected and Uncorrected Errors (DUE) relying on error detection techniques already available in commodity hardware. Detection operates at the memory page ...
    • Exploiting asynchrony from exact forward recovery for DUE in iterative solvers 

      Jaulmes, Luc; Casas, Marc; Moretó Planas, Miquel; Ayguadé Parra, Eduard; Labarta Mancho, Jesús José; Valero Cortés, Mateo (Association for Computing Machinery (ACM), 2015)
      Text en actes de congrés
      Accés obert
      This paper presents a method to protect iterative solvers from Detected and Uncorrected Errors (DUE) relying on error detection techniques already available in commodity hardware. Detection operates at the memory page ...