Exploració per autor "Valero Cortés, Mateo"
Ara es mostren els items 56-75 de 357
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Balancing HPC applications through smart allocation of resources in MT processors
(Institute of Electrical and Electronics Engineers (IEEE), 2008)
Text en actes de congrés
Accés obertMany studies have shown that load imbalancing causes significant performance degradation in High Performance Computing (HPC) applications. Nowadays, Multi-Threaded (MT1) processors are widely used in HPC for their good ... -
Bandwidth of crossbar and multiple-bus connections for multiprocessors
(1982-12)
Article
Accés obertIn this paper we compare the effective bandwidth in a multiprocessor with shared memory using as interconnection networks the crossbar or the multiple-bus. We consider a system with N processors and N memory modules, in ... -
Barcelona Supercomputing Center
(2019-05-29)
Audiovisual
Accés obertLa Conferència tracta sobre aquest centre pioner de la supercomputació a Catalunya. La seva naturalesa és doble: d'una banda és un centre d'investigació format per més de tres-cents científics i, per una altra, és un ... -
Better branch prediction through prophet/critic hybrids
(2005-01)
Article
Accés obertThe prophet/critic hybrid conditional branch predictor has two component predictors. The prophet uses a branch's history to predict its direction. We call this prediction and the ones for branches following it the branch ... -
Branch classification to control instruction fetch in simultaneous multithreaded architectures
(Institute of Electrical and Electronics Engineers (IEEE), 2002)
Text en actes de congrés
Accés obertIn simultaneous multithreaded architectures many separate threads are running concurrently, sharing processor resources, thereby realizing a high utilization rate of the available hardware. However, this also implies that ... -
BSC contributions in energy-aware resource management for large scale distributed systems
(2010)
Text en actes de congrés
Accés obertThis paper introduces the work being carried out at Barcelona Supercomputing Center in the area of Green Computing. We have been working in resource management for a long time and recently we included the energy parameter ... -
BSLD threshold driven parallel job scheduling for energy efficient HPC centers
(2009)
Report de recerca
Accés obertRecently, power awareness in high performance computing (HPC) community has increased significantly. While CPU power reduction of HPC applications using Dynamic Voltage Frequency Scaling (DVFS) has been explored thoroughly, ... -
BSLD threshold driven power management policy for HPC centers
(Institute of Electrical and Electronics Engineers (IEEE), 2010)
Text en actes de congrés
Accés obertIn this paper, we propose a power-aware parallel job scheduler assuming DVFS enabled clusters. A CPU frequency assignment algorithm is integrated into the well established EASY backfilling job scheduling policy. Running a ... -
CATA: Criticality aware task acceleration for multicore processors
(Institute of Electrical and Electronics Engineers (IEEE), 2016)
Text en actes de congrés
Accés obertManaging criticality in task-based programming models opens a wide range of performance and power optimization opportunities in future manycore systems. Criticality aware task schedulers can benefit from these opportunities ... -
Chained in-order/out-of-order doublecore architecture
(Institute of Electrical and Electronics Engineers (IEEE), 2005)
Text en actes de congrés
Accés obertComplexity is one of the most important problems facing microarchitects. It is exacerbated by the application of optimizations, by scaling to higher issue widths and, in general, by increasing the size of microprocessor ... -
Characterizing the communication demands of the Graph500 benchmark on a commodity cluster
(Institute of Electrical and Electronics Engineers (IEEE), 2014)
Text en actes de congrés
Accés obertBig Data applications have gained importance over the last few years. Such applications focus on the analysis of huge amounts of unstructured information and present a series of differences with traditional High Performance ... -
Characterizing the resource-sharing levels of the UltraSparc T2 processor
(Association for Computing Machinery (ACM), 2009)
Text en actes de congrés
Accés restringit per política de l'editorialThread level parallelism (TLP) has become a popular trend to improve processor performance, overcoming the limitations of extracting instruction level parallelism. Each TLP paradigm, such as Simultaneous Multithreading or ... -
Circuit design of a dual-versioning L1 data cache for optimistic concurrency
(2011)
Report de recerca
Accés obertThis paper proposes a novel L1 data cache design with dual-versioning SRAM cells (dvSRAM) for chip multi-processors (CMP) that implement optimistic concurrency proposals. In this new cache architecture, each dvSRAM cell ... -
Clock gate on abort: Towards energy-efficient hardware transactional memory
(Institute of Electrical and Electronics Engineers (IEEE), 2009)
Text en actes de congrés
Accés obertTransactional Memory (TM) is an emerging technology which promises to make parallel programming easier compared to earlier lock based approaches. However, as with any form of speculation, Transactional Memory too wastes a ... -
Code layout optimizations for transaction processing workloads
(Institute of Electrical and Electronics Engineers (IEEE), 2001)
Text en actes de congrés
Accés obertCommercial applications such as databases and Web servers constitute the most important market segment for high-performance servers. Among these applications, on-line transaction processing (OLTP) workloads provide a ... -
Code semantic-aware runahead threads
(2009-09)
Text en actes de congrés
Accés restringit per política de l'editorialMemory-intensive threads can hoard shared re- sources without making progress on a multithreading processor (SMT), thereby hindering the overall system performance. A recent promising solution to overcome this important ... -
CODOMs: Protecting software with code-centric memory domains
(Institute of Electrical and Electronics Engineers (IEEE), 2014)
Text en actes de congrés
Accés restringit per política de l'editorialToday's complex software systems are neither secure nor reliable. The rudimentary software protection primitives provided by current hardware forces systems to run many distrusting software components (e.g., procedures, ... -
Coherence protocol for transparent management of scratchpad memories in shared memory manycore architectures
(Association for Computing Machinery (ACM), 2015)
Text en actes de congrés
Accés obertThe increasing number of cores in manycore architectures causes important power and scalability problems in the memory subsystem. One solution is to introduce scratchpad memories alongside the cache hierarchy, forming a ... -
Command vector memory systems: high performance at low cost
(Institute of Electrical and Electronics Engineers (IEEE), 1998)
Text en actes de congrés
Accés obertThe focus of this paper is on designing both a low cost and high performance, high bandwidth vector memory system that takes advantage of modern commodity SDRAM memory chips. To successfully extract the full bandwidth from ... -
Commit on overflow
(2014)
Report de recerca
Accés obertCurrent commercial CPUs have hardware support for speculative lock elision (SLE). SLE tries to elide the lock by speculatively executing lock protected critical section. If the speculation fails, SLE acquires the lock and ...
