Exploració per autor "Llaberia Griñó, José M."
Ara es mostren els items 18-34 de 34
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On automatic loop data-mapping for distributed-memory multiprocessors
Torres Viñals, Jordi; Ayguadé Parra, Eduard; Labarta Mancho, Jesús José; Llaberia Griñó, José M.; Valero Cortés, Mateo (Springer, 1991)
Text en actes de congrés
Accés obertIn this paper we present a unified approach for compiling programs for Distributed-Memory Multiprocessors (DMM). Parallelization of sequential programs for DMM is much more difficult to achieve than for shared memory systems ... -
On reducing misspeculations on a pipelined scheduler
Gran Tejero, Ruben; Morancho Llena, Enrique; Olivé Durán, Ángel; Llaberia Griñó, José M. (2009)
Text en actes de congrés
Accés obertPipelining the scheduling logic, which exposes and exploits the instruction level parallelism, degrades processor performance. In a 4-issue processor, our evaluations show that pipelining the scheduling logic over two ... -
Partitioning: an essential step in mapping algorithms into systolic array processors
Navarro Guerrero, Juan José; Llaberia Griñó, José M.; Valero Cortés, Mateo (1987-07)
Article
Accés obertThe efficient solution of a large problem on a small systolic array requires good partitioning techniques to split the problem into subproblems that fit the array size. -
Pronóstico de capacidad efectiva y prestaciones en una cache no volátil de último nivel
Escuín Blasco, Carlos; Monreal Arnal, Teresa; Llaberia Griñó, José M.; Ibáñez Marín, Pablo Enrique; Viñals Yúfera, Victor (Sociedad de Arquitectura y Tecnología de Computadores (SARTECO), 2021)
Text en actes de congrés
Accés obertLa degradación debida a las escrituras que sufren las bitcells implementadas con tecnologi´as de memoria no volátil (NVM) es uno de los principales escollos que se presentan a la hora de construir la cache de último nivel ... -
ReD: A policy based on reuse detection for demanding block selection in last-level Caches
Díaz Maag, Javier; Ibáñez Marín, Pablo Enrique; Monreal Arnal, Teresa; Viñals Yúfera, Víctor; Llaberia Griñó, José M. (2017)
Text en actes de congrés
Accés obertIn this paper, we propose a new block selection policy for Last-Level Caches (LLCs) that decides, based on Reuse Detection, whether a block coming from main memory is inserted, or not, in the LLC. The proposed policy, ... -
ReD: A reuse detector for content selection in exclusive shared last-level caches
Díaz, Javier; Monreal Arnal, Teresa; Ibáñez Marín, Pablo Enrique; Llaberia Griñó, José M.; Viñals Yúfera, Víctor (Elsevier, 2019-03)
Article
Accés obertThe reference stream reaching a chip multiprocessor Shared Last-Level Cache (SLLC) shows poor temporal locality, making conventional cache management policies inefficient. Few proposals address this problem for exclusive ... -
Reducción de la degradación y el conflicto en las redes de interconexión para sistemas multiprocesadores
Llaberia Griñó, José M.; Labarta Mancho, Jesús José; Herrada Lillo, Enrique; Valero Cortés, Mateo (Asociación Española de Informática y Automática, 1985)
Text en actes de congrés
Accés obertUno de los parámetros causante de una disminuación potencial de la eficiencia de un sistema multiprocesador es el tiempo de respuesta del subsistemas de memoria. En este trabajo se presentan diversas técnicas que mejoran ... -
Reducing branch delay to zero in pipelined processors
González Colás, Antonio María; Llaberia Griñó, José M. (1993-03)
Article
Accés obertA mechanism to reduce the cost of branches in pipelined processors is described and evaluated. It is based on the use of multiple prefetch, early computation of the target address, delayed branch, and parallel execution ... -
Reuse Detector: improving the management of STT-RAM SLLCs
Rodríguez Rodríguez, Roberto; Díaz Maag, Javier; Castro, Fernando; Ibáñez Marín, Pablo Enrique; Chaver Martínez, Daniel A.; Viñals Yúfera, Víctor; Sáez Alcaide, Juan Carlos; Prieto Matías, Manuel; Piñuel, Luis; Monreal Arnal, Teresa; Llaberia Griñó, José M. (2018-06-01)
Article
Accés obertVarious constraints of Static Random Access Memory (SRAM) are leading to consider new memory technologies as candidates for building on-chip shared last-level caches (SLLCs). Spin-Transfer Torque RAM (STT-RAM) is currently ... -
Shared queues in buffered multistage interconnection networks
Domingo Pascual, Jordi; Labarta Mancho, Jesús José; Casals, Olga; Llaberia Griñó, José M.; Valero Cortés, Mateo (1988-01)
Report de recerca
Accés obertThis paper analyses the behaviour of a normal buffered delta network and as a result proposes the use of a shared queue instead of the two queues of the usual switching elements. The performance of the networks with ... -
Solving matrix problems with no size restriction on a systolic array processor
Navarro Guerrero, Juan José; Llaberia Griñó, José M.; Valero Cortés, Mateo (1986)
Report de recerca
Accés obertIn this paper we propose several data structures partitioning and transformation schemes, in order to get an efficient execution of various matrix algorithms without any size resriction. The following matrix operations are ... -
Source code transformations for efficient SIMD code generation
Berna Juan, Alejandro; Jiménez Castells, Marta; Llaberia Griñó, José M. (2012-01)
Report de recerca
Accés obertDespite the effort inverted the last years in commercial compilers to generate efficient SIMD instructions based code sequences from conventional sequential programs, the small numbers of compilers that can automatically ... -
Source-to-Source transformations for efficient SIMD code generation
Berna Juan, Alejandro; Jiménez Castells, Marta; Llaberia Griñó, José M. (2011)
Text en actes de congrés
Accés obertIn the last years, there has been much effort in commercial compilers to generate efficient SIMD instructions-based code sequences from conventional sequential programs. However, the small numbers of compilers that can ... -
STT-RAM memory hierarchy designs aimed to performance, reliability and energy consumption
Escuín Blasco, Carlos; Monreal Arnal, Teresa; Llaberia Griñó, José M.; Viñals Yúfera, Victor; Ibáñez Marín, Pablo (European Network of Excellence on High Performance and Embedded Architecture and Compilation (HiPEAC), 2019)
Comunicació de congrés
Accés obertCurrent applications demand larger on-chip memory capacity since off-chip memory accesses be-come a bottleneck. However, if we want to achieve this by scaling down the transistor size of SRAM-based Last-Level Caches (LLCs) ... -
Systematic design of two level pipelined systolic arrays with data contraflow
Valero García, Miguel; Navarro Guerrero, Juan José; Llaberia Griñó, José M.; Valero Cortés, Mateo (1988)
Text en actes de congrés
Accés obertMany systolic algorithms and related design methodologies have been recently proposed. Frecuently, in these systolic algorithms practical considerations are not taken into account. Equitatively distributed load between ... -
Transformation of systolic algorithms for interleaving partitions
Fernández Jiménez, Agustín; Llaberia Griñó, José M.; Navarro Guerrero, Juan José; Valero García, Miguel (1990)
Text en actes de congrés
Accés obertA systematic method to map systolizable problems onto multicomputers is presented in this paper. A systolizable problem is a problem for which it is possible to design a Systolic Algorithm. This method selects and transforms ... -
Vectorized register tiling
Berna Juan, Alejandro; Jiménez Castells, Marta; Llaberia Griñó, José M. (2012-01)
Report de recerca
Accés obertIn the last years, there has been much effort in commercial compilers (icc, gcc) to exploit efficiently the SIMD capabilities and the memory hierarchy that the current processors offer. However, the small numbers of compilers ...