Ara es mostren els items 10-29 de 34

    • Implementation of systolic algorithms using pipelined functional units 

      Valero García, Miguel; Navarro Guerrero, Juan José; Llaberia Griñó, José M.; Valero Cortés, Mateo (1990)
      Text en actes de congrés
      Accés obert
      The authors present a method to implement systolic algorithms (SAs) using pipelined functional units (PFUs). This kind of unit makes it possible to improve the throughput of a processor because of the possibility of ...
    • Increasing the number of strides for conflict-free vector access 

      Valero Cortés, Mateo; Lang, Tomas; Llaberia Griñó, José M.; Peiron Guàrdia, Montse; Ayguadé Parra, Eduard; Navarro Guerrero, Juan José (1992-05)
      Article
      Accés obert
      Address transformation schemes, such as skewing and linear transformations, have been proposed to achieve conflict-free vector access for some strides in vector processors with multi-module memories. In this paper, we ...
    • Introducción al compilador Open64/ORC 

      Santamaria Barnadas, Eduard; Jiménez Castells, Marta; Fernández Jiménez, Agustín; Llaberia Griñó, José M. (2003-05-13)
      Report de recerca
      Accés obert
    • Keeping control transfer instructions out of the pipeline in architectures without condition codes 

      Cortadella, Jordi; Llaberia Griñó, José M.; González Colás, Antonio María (1987-05)
      Report de recerca
      Accés obert
      The execution of branch instructions involves a loss of performance in pipelined processors. In this paper we present a mechanism for executing this kind of instruction with a zero delay. This mechanism has been proposed ...
    • L2C2: Last-level compressed-contents non-volatile cache and a procedure to forecast performance and lifetime 

      Escuín Blasco, Carlos; Ibáñez Marín, Pablo; Navarro, Denis; Monreal Arnal, Teresa; Llaberia Griñó, José M.; Viñals Yúfera, Victor (Public Library of Science (PLOS), 2023-02-07)
      Article
      Accés obert
      Several emerging non-volatile (NV) memory technologies are rising as interesting alternatives to build the Last-Level Cache (LLC). Their advantages, compared to SRAM memory, are higher density and lower static power, but ...
    • Leveraging data compression for performance-efficient and long-lasting NVM-based last-level cache 

      Escuín Blasco, Carlos; Ali Khan, Asif; Ibáñez Marín, Pablo Enrique; Monreal Arnal, Teresa; Navarro, Denis; Llaberia Griñó, José M.; Castrillón, Jerónimo; Viñals Yúfera, Victor (University of California, Los Angeles (UCLA), 2023)
      Comunicació de congrés
      Accés obert
      Non-volatile memory (NVM) technologies are interesting alternatives for building on-chip Last-Level Caches (LLCs). Their advantages, compared to SRAM memory, are higher density and lower static power, but each write operation ...
    • MNEMOSENE++: Scalable multi-tile design with enhanced buffering and VGSOT-MRAM based compute-in-memory crossbar array 

      Escuín Blasco, Carlos; García Redondo, Fernando; Zahedi, Mahdi; Ibáñez Marín, Pablo Enrique; Monreal Arnal, Teresa; Viñals Yúfera, Victor; Llaberia Griñó, José M.; Myers, James; Ryckaert, Julien; Biswas, Dwaipayan; Catthoor, Francky (Institute of Electrical and Electronics Engineers (IEEE), 2023)
      Comunicació de congrés
      Accés obert
      This paper optimizes the MNEMOSENE architecture, a compute-in-memory (CiM) tile design integrating computation and storage for increased efficiency. We identify and address bottlenecks in the Row Data (RD) buffer that cause ...
    • Near-optimal replacement policies for shared caches in multicore processors 

      Díaz Maag, Javier; Ibáñez Marín, Pablo; Monreal Arnal, Teresa; Viñals Yúfera, Victor; Llaberia Griñó, José M. (2021-10)
      Article
      Accés obert
      An optimal replacement policy that minimizes the miss rate in a private cache was proposed several decades ago. It requires knowing the future access sequence the cache will receive. There is no equivalent for shared caches ...
    • On automatic loop data-mapping for distributed-memory multiprocessors 

      Torres Viñals, Jordi; Ayguadé Parra, Eduard; Labarta Mancho, Jesús José; Llaberia Griñó, José M.; Valero Cortés, Mateo (Springer, 1991)
      Text en actes de congrés
      Accés obert
      In this paper we present a unified approach for compiling programs for Distributed-Memory Multiprocessors (DMM). Parallelization of sequential programs for DMM is much more difficult to achieve than for shared memory systems ...
    • On reducing misspeculations on a pipelined scheduler 

      Gran Tejero, Ruben; Morancho Llena, Enrique; Olivé Durán, Ángel; Llaberia Griñó, José M. (2009)
      Text en actes de congrés
      Accés obert
      Pipelining the scheduling logic, which exposes and exploits the instruction level parallelism, degrades processor performance. In a 4-issue processor, our evaluations show that pipelining the scheduling logic over two ...
    • Partitioning: an essential step in mapping algorithms into systolic array processors 

      Navarro Guerrero, Juan José; Llaberia Griñó, José M.; Valero Cortés, Mateo (1987-07)
      Article
      Accés obert
      The efficient solution of a large problem on a small systolic array requires good partitioning techniques to split the problem into subproblems that fit the array size.
    • Pronóstico de capacidad efectiva y prestaciones en una cache no volátil de último nivel 

      Escuín Blasco, Carlos; Monreal Arnal, Teresa; Llaberia Griñó, José M.; Ibáñez Marín, Pablo Enrique; Viñals Yúfera, Victor (Sociedad de Arquitectura y Tecnología de Computadores (SARTECO), 2021)
      Text en actes de congrés
      Accés obert
      La degradación debida a las escrituras que sufren las bitcells implementadas con tecnologi´as de memoria no volátil (NVM) es uno de los principales escollos que se presentan a la hora de construir la cache de último nivel ...
    • ReD: A policy based on reuse detection for demanding block selection in last-level Caches 

      Díaz Maag, Javier; Ibáñez Marín, Pablo Enrique; Monreal Arnal, Teresa; Viñals Yúfera, Víctor; Llaberia Griñó, José M. (2017)
      Text en actes de congrés
      Accés obert
      In this paper, we propose a new block selection policy for Last-Level Caches (LLCs) that decides, based on Reuse Detection, whether a block coming from main memory is inserted, or not, in the LLC. The proposed policy, ...
    • ReD: A reuse detector for content selection in exclusive shared last-level caches 

      Díaz, Javier; Monreal Arnal, Teresa; Ibáñez Marín, Pablo Enrique; Llaberia Griñó, José M.; Viñals Yúfera, Víctor (Elsevier, 2019-03)
      Article
      Accés obert
      The reference stream reaching a chip multiprocessor Shared Last-Level Cache (SLLC) shows poor temporal locality, making conventional cache management policies inefficient. Few proposals address this problem for exclusive ...
    • Reducción de la degradación y el conflicto en las redes de interconexión para sistemas multiprocesadores 

      Llaberia Griñó, José M.; Labarta Mancho, Jesús José; Herrada Lillo, Enrique; Valero Cortés, Mateo (Asociación Española de Informática y Automática, 1985)
      Text en actes de congrés
      Accés obert
      Uno de los parámetros causante de una disminuación potencial de la eficiencia de un sistema multiprocesador es el tiempo de respuesta del subsistemas de memoria. En este trabajo se presentan diversas técnicas que mejoran ...
    • Reducing branch delay to zero in pipelined processors 

      González Colás, Antonio María; Llaberia Griñó, José M. (1993-03)
      Article
      Accés obert
      A mechanism to reduce the cost of branches in pipelined processors is described and evaluated. It is based on the use of multiple prefetch, early computation of the target address, delayed branch, and parallel execution ...
    • Reuse Detector: improving the management of STT-RAM SLLCs 

      Rodríguez Rodríguez, Roberto; Díaz Maag, Javier; Castro, Fernando; Ibáñez Marín, Pablo Enrique; Chaver Martínez, Daniel A.; Viñals Yúfera, Víctor; Sáez Alcaide, Juan Carlos; Prieto Matías, Manuel; Piñuel, Luis; Monreal Arnal, Teresa; Llaberia Griñó, José M. (2018-06-01)
      Article
      Accés obert
      Various constraints of Static Random Access Memory (SRAM) are leading to consider new memory technologies as candidates for building on-chip shared last-level caches (SLLCs). Spin-Transfer Torque RAM (STT-RAM) is currently ...
    • Shared queues in buffered multistage interconnection networks 

      Domingo Pascual, Jordi; Labarta Mancho, Jesús José; Casals, Olga; Llaberia Griñó, José M.; Valero Cortés, Mateo (1988-01)
      Report de recerca
      Accés obert
      This paper analyses the behaviour of a normal buffered delta network and as a result proposes the use of a shared queue instead of the two queues of the usual switching elements. The performance of the networks with ...
    • Solving matrix problems with no size restriction on a systolic array processor 

      Navarro Guerrero, Juan José; Llaberia Griñó, José M.; Valero Cortés, Mateo (1986)
      Report de recerca
      Accés obert
      In this paper we propose several data structures partitioning and transformation schemes, in order to get an efficient execution of various matrix algorithms without any size resriction. The following matrix operations are ...
    • Source code transformations for efficient SIMD code generation 

      Berna Juan, Alejandro; Jiménez Castells, Marta; Llaberia Griñó, José M. (2012-01)
      Report de recerca
      Accés obert
      Despite the effort inverted the last years in commercial compilers to generate efficient SIMD instructions based code sequences from conventional sequential programs, the small numbers of compilers that can automatically ...