Ara es mostren els items 29-48 de 51

    • Parametric Failure Analysis of Embedded SRAMs using Fast & Accurate Dynamic Analysis 

      Vatajelu, Elena Ioana; Panagopoulos, Georgios; Roy, Kaushik; Figueras Pàmies, Joan (IEEE Press. Institute of Electrical and Electronics Engineers, 2010)
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    • Post-Bond test of through-silicon vias with open defects 

      Rodríguez Montañés, Rosa; Arumi Delgado, Daniel; Figueras Pàmies, Joan (2014)
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      Through Silicon Vias (TSVs) are critical elements in three dimensional integrated circuits (3-D ICs) and are susceptible to undergo defects at different stages: during their own fabrication, the bonding stage or during ...
    • Postbond test of through-silicon vias with resistive open defects 

      Rodríguez Montañés, Rosa; Arumi Delgado, Daniel; Figueras Pàmies, Joan (2019-07-17)
      Article
      Accés obert
      Through-silicon vias (TSVs) technology has attracted industry interest as a way to achieve high bandwidth, and short interconnect delays in nanometer three-dimensional integrated circuits (3-D ICs). However, TSVs are ...
    • Power-aware voltage tuning for STT-MRAM reliability 

      Vatajelu, Elena Ioana; Rodríguez Montañés, Rosa; Di Carlo, Stefano; Renovell, Michel; Prinetto, Paolo; Figueras Pàmies, Joan (Institute of Electrical and Electronics Engineers (IEEE), 2015)
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      One of the most promising emerging memory technologies is the Spin-Transfer-Torque Magnetic Random Access Memory (STT-MRAM), due to its high speed, high endurance, low area, low power consumption, and good scaling capability. ...
    • Prebond testing of weak defects in TSVs 

      Arumi Delgado, Daniel; Rodríguez Montañés, Rosa; Figueras Pàmies, Joan (2015-08-07)
      Article
      Accés restringit per política de l'editorial
      Through-silicon vias (TSVs) are critical elements in 3-D integrated circuits susceptible to defects during fabrication and lifetime. It is desirable to detect defective TSVs in the early steps of the fabrication process ...
    • Process variability in sub-16nm bulk CMOS technology 

      Rubio Sola, Jose Antonio; Figueras Pàmies, Joan; Vatajelu, Elena Ioana; Canal Corretger, Ramon (2012-03-01)
      Report de recerca
      Accés obert
      The document is part of deliverable D3.6 of the TRAMS Project (EU FP7 248789), of public nature, and shows and justifies the levels of variability used in the research project for sub-18nm bulk CMOS technologies.
    • Quality metrics for mixed-signal indirect testing 

      Gómez Pau, Álvaro; Balado Suárez, Luz María; Figueras Pàmies, Joan (2014)
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    • Quiescent current analysis and experimentation of defective CMOS circuits 

      Segura, J A; Champac, V H; Rodríguez Montañés, Rosa; Figueras Pàmies, Joan; Rubio Sola, Jose Antonio (1992-12)
      Article
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      Physical defects widely encountered in today's CMOS processes (bridges, gate oxide short (gas) and floating gates) are modeled taking into account the topology of the defective circuit and the parameters of the technology. ...
    • Read/write robustness estimation metrics for spin transfer torque (STT) MRAM cell 

      Vatajelu, Elena Ioana; Rodríguez Montañés, Rosa; Indaco, Marco; Renovell, Michel; Prinetto, Paolo; Figueras Pàmies, Joan (Institute of Electrical and Electronics Engineers (IEEE), 2015)
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      The rapid development of low power, high density, high performance SoCs has pushed the embedded memories to their limits and opened the field to the development of emerging memory technologies. The Spin- Transfer-Torque ...
    • Redes de ordenadores, redes de sistemas, sistemas distribuidos 

      Alabau Muñoz, Antonio; Figueras Pàmies, Joan (Asociación de Técnicos de Informática, 1980-11)
      Article
      Accés obert
    • Reliability estimation at block-level granularity of spin-transfer-torque MRAMs 

      Di Carlo, Stefano; Indaco, Marco; Prinetto, Paolo; Vatajelu, Elena Ioana; Rodríguez Montañés, Rosa; Figueras Pàmies, Joan (Institute of Electrical and Electronics Engineers (IEEE), 2014)
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      In recent years, the Spin-Transfer-Torque Magnetic Random Access Memory (STT-MRAM) has emerged as a promising choice for embedded memories due to its reduced read/write latency and high CMOS integration capability. Under ...
    • Robustness of SRAM to Power Supply Noise during Leakage Power Saving in DVS 

      Vatajelu, Elena Ioana; Renovell, Michel; Figueras Pàmies, Joan (IEEE Press. Institute of Electrical and Electronics Engineers, 2010)
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    • SRAM cell stability metric under transient voltage noise 

      Vatajelu, Elena Ioana; Gómez Pau, Álvaro; Renovell, Michel; Figueras Pàmies, Joan (2013-12-20)
      Article
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    • SRAM stability metric under transient noise 

      Vatajelu, Elena Ioana; Gómez Pau, Álvaro; Renovell, Michel; Figueras Pàmies, Joan (2012)
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      Accés obert
      ventional way to analyze the robustness of an SRAM bit cell is to quantify its immunity to static noise. The static immunity to disturbances like process and mi smatch variations, bulk noises, supply rings variations, ...
    • Statistical analysis of SRAM aarametric failure under supply voltage scaling 

      Vatajelu, Elena Ioana; Figueras Pàmies, Joan (IEEE Computer Society Publications, 2010)
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    • Structural and functional fault-tolerance evaluation of local area networks 

      Carrasco, Juan A.; Figueras Pàmies, Joan (1985)
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      Fault tolerance attributes of Local Area Networks (LAN) have been evaluated in their structural (topologies) and functional (protocols) aspects. In relation to structural faults, a fault model has been developed and five ...
    • STT-MRAM cell reliability evaluation under process, voltage and temperature (PVT) variations 

      Vatajelu, Elena Ioana; Rodríguez Montañés, Rosa; Indaco, Marco; Prinetto, Paolo; Figueras Pàmies, Joan (Institute of Electrical and Electronics Engineers (IEEE), 2015)
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      The CMOS based memories are facing major issues with technology scaling, such as decreased reliability and increased leakage power. A point will be reached when the technology scaling issues will overweight the benefits. ...
    • Synthesis of IDDQ-Testable Circuits: Integrating Built-in Current Sensors 

      Wunderlich, H J; Herzog, M; Figueras Pàmies, Joan; Carrasco, Juan A.; Calderón, A (1995)
      Text en actes de congrés
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      "On-Chip" I_{DDQ} testing by the incorporation of Built-In Current (BIC) sensors has some advantages over "off-chip" techniques. However, the integration of sensors poses analog design problems which are hard to be solved ...
    • Test of dual axis accelerometers based on specifications compliance 

      Gómez Pau, Álvaro; Balado Suárez, Luz María; Figueras Pàmies, Joan (Universidad de Navarra, 2013)
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    • Testing IC accelerometers using Lissajous compositions 

      Gómez Pau, Álvaro; Balado Suárez, Luz María; Figueras Pàmies, Joan (2011)
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      Micro Electro Mechanical devices (MEMs) have widened their range of applications in a spectacular way in the last years. Reliability of MEMs devices is one of the areas that need to be improved to achieve high volume ...