Ara es mostren els items 35-44 de 44

    • Reliability study on technology trends beyond 20nm 

      Amat Bertran, Esteve; Calomarde Palomino, Antonio; Rubio Sola, Jose Antonio (Lodz University of Technology, 2013)
      Text en actes de congrés
      Accés restringit per política de l'editorial
      In this work, an assessment of different technology trends (planar CMOS, FinFET and III-V MOSFETs) has been carried out in front of some different reliability scenarios (variability and soft errors). The logic circuits ...
    • Review on suitable eDRAM configurations for next nano-metric electronics era 

      Amat, Esteve; Canal Corretger, Ramon; Calomarde Palomino, Antonio; Rubio Sola, Jose Antonio (2018-03)
      Article
      Accés obert
      We summarize most of our studies focused on the main reliability issues that can threat the gain-cells eDRAM behavior when it is simulated at the nano-metric device range has been collected in this review. So, to outperform ...
    • Robust sequential circuits design technique for low voltage and high noise scenarios 

      García Leyva, Lancelot; Rivera Dueñas, Juan; Calomarde Palomino, Antonio; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio (2016)
      Text en actes de congrés
      Accés obert
      All electronic processing components in future deep nanotechnologies will exhibit high noise level and/ or low S/N ratios because of the extreme voltage reduction and the nearly erratic nature of such devices. ...
    • SET and noise fault tolerant circuit design techniques: application to 7 nm FinFET 

      Calomarde Palomino, Antonio; Amat Bertran, Esteve; Moll Echeto, Francisco de Borja; Vigara Campmany, Julio Enrique; Rubio Sola, Jose Antonio (2014-04-01)
      Article
      Accés obert
      In the near future of high component density and low-power technologies, soft errors occurring not only in memory systems and latches but also in the combinational parts of logic circuits will seriously affect the reliable ...
    • Suitability of FinFET introduction into eDRAM cells for operate at sub-threshold level 

      Amat, Esteve; Calomarde Palomino, Antonio; Canal Corretger, Ramon; Rubio Sola, Jose Antonio (Institute of Electrical and Electronics Engineers (IEEE), 2017)
      Comunicació de congrés
      Accés restringit per política de l'editorial
      This paper explores the feasibility, in terms of performance and reliability, of gain-cell embedded DRAM (eDRAM) to be operative at sub-threshold range, when they are implemented with 10 nm FinFET devices. The use of ...
    • Turtle Logic: A new probabilistic design methodology of nanoscale digital circuits 

      García Leyva, Lancelot; Calomarde Palomino, Antonio; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio (IEEE Press. Institute of Electrical and Electronics Engineers, 2010)
      Text en actes de congrés
      Accés obert
      As devices and operating voltages are scaled down, future circuits will be plagued by higher soft error rates, reduced noise margins and defective devices. A key challenge for the future technologies is to retain circuit ...
    • Turtle logic: Novel IC digital probabilistic design methodology 

      García Leyva, Lancelot; Rubio Sola, Jose Antonio; Moll Echeto, Francisco de Borja; Calomarde Palomino, Antonio (2010)
      Text en actes de congrés
      Accés obert
      Future electronic devices are expected to operate at lower voltage supply to save power, especially in ultimate and new technologies. The resulting reduction of logic levels approaches the thermal noise limit, and ...
    • Two examples of approximate arithmetic to reduce hardware complexity and power consumption 

      Fornt Mas, Jordi; Jin, Leixin; Etxezarreta, Imanol; Fontova, Pau; Altet Sanahujes, Josep; Calomarde Palomino, Antonio; Morancho Llena, Enrique; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio (Institute of Electrical and Electronics Engineers (IEEE), 2022)
      Comunicació de congrés
      Accés obert
      As the end of Moore's Law approaches, electronic system designers must find ways to keep up with the ever increasing computational demands of the modern era. Some computationally intensive applications, such as multimedia ...
    • Variability impact on on-chip memory data paths 

      Amat Bertran, Esteve; Calomarde Palomino, Antonio; Canal Corretger, Ramon; Rubio Sola, Jose Antonio (2014)
      Comunicació de congrés
      Accés obert
      Process variations have a large impact on device and circuit reliability and performance. Few studies are focused on their impact on more complex systems, as for example their influence in a data path. In our study, the ...
    • Variation tolerant self-adaptive clock generation architecture based on a ring oscillator 

      Pérez Puigdemont, Jordi; Calomarde Palomino, Antonio; Moll Echeto, Francisco de Borja (Institute of Electrical and Electronics Engineers (IEEE), 2012)
      Comunicació de congrés
      Accés obert
      In this work we propose a self-adaptive clock based on a ring oscillator as the solution for the increasing uncertainty in the critical path delay. This increase in uncertainty forces to add more safety margins to the ...