Exploració per autor "Calomarde Palomino, Antonio"
Ara es mostren els items 25-44 de 44
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High level spectral-based análisis of power concumption in DSP's systems
Calomarde Palomino, Antonio; Mateo Peña, Diego; Rubio Sola, Jose Antonio (Institute of Electrical and Electronics Engineers (IEEE), 2006)
Text en actes de congrés
Accés restringit per política de l'editorialIn this paper, an efficient technique to evaluate temporal correlation and transition activity at high level in DSP systems is presented. The method is based on the spectral distribution of signals and has the advantage ... -
Impact of finfet and III-V/Ge technology on logic and memory cell behavior
Amat Bertran, Esteve; Calomarde Palomino, Antonio; García Almudéver, Carmen; Aymerich Capdevila, Nivard; Canal Corretger, Ramon; Rubio Sola, Jose Antonio (2013-11-20)
Article
Accés restringit per política de l'editorialIn this work, we assess the performance of a ring oscillator and a DRAM cell when they are implemented with different technologies (planar CMOS, FinFET and III-V MOSFETs), and subjected to different reliability scenarios ... -
IMPLEMENTACIÓ DE SISTEMES AUDIOVISUALS (Examen 2n quadrimestre, 1r parcial)
Calomarde Palomino, Antonio (Universitat Politècnica de Catalunya, 2013-04-18)
Examen
Accés restringit a la comunitat UPC -
IMPLEMENTACIÓ DE SISTEMES AUDIOVISUALS (Examen 2n quadrimestre, 2n parcial)
Calomarde Palomino, Antonio (Universitat Politècnica de Catalunya, 2013-06-10)
Examen
Accés restringit a la comunitat UPC -
IMPLEMENTACIÓ DE SISTEMES AUDIOVISUALS (Examen 2n quadrimestre, 2n parcial)
Calomarde Palomino, Antonio (Universitat Politècnica de Catalunya, 2012-06-18)
Examen
Accés restringit a la comunitat UPC -
Influence of punch trough stop layer and well depths on the robustness of bulk FinFETs to heavy ions impact
Calomarde Palomino, Antonio; Manich Bou, Salvador; Rubio Sola, Jose Antonio; Gamiz, Francisco (Institute of Electrical and Electronics Engineers (IEEE), 2022-05-02)
Article
Accés obertThis study analyzes the effects of the punch-through stop (PTS) layer and well depth in a bulk FinFET SRAM cell on the fraction of charge generated by an ion impact that is collected by the FinFET channel. More than 1700 ... -
Introducing autonomous vehicles into an unergraduate engineering course
Blesa Izquierdo, Joaquim; Ponsa Asensio, Pere; Calomarde Palomino, Antonio; García Abián, Jonathan; Repecho del Corral, Víctor (Universitat Politècnica de Catalunya, 2022-09)
Text en actes de congrés
Accés obertAutonomous vehicles (AVs) are of great interest for the automotive industry and are expected to revolutionize mobility and public transportation. The university can contribute to the design and development of autonomous ... -
New redundant logic design concept for high noise and low voltage scenarios
García Leyva, Lancelot; Andrade Miceli, Dennis Michael; Gómez Fernández, Sergio; Calomarde Palomino, Antonio; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio (2011-12)
Article
Accés restringit per política de l'editorialThis paper presents a new redundant logia design concept named Turtle Logic(TL).It is a new probabilistic logic method based on port redundancy and complementary data, oriented toward emerging technologies beyond CMOS, ... -
Novel redundant logic design for noisy low voltage scenarios
García Leyva, Lancelot; Calomarde Palomino, Antonio; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio (2013)
Text en actes de congrés
Accés restringit per política de l'editorialThe concept worked in this paper named Turtle Logic (TL) is a probabilistic logic method based on port redundancy and complementary data, oriented to emerging CMOS technologies and beyond, where the thermal noise could be ... -
Optimization of FinFET-based gain cells for low power sub-vt embedded drams
Amat, Esteve; Calomarde Palomino, Antonio; Canal Corretger, Ramon; Rubio Sola, Jose Antonio (2018-06-01)
Article
Accés obertSub-threshold circuits (sub-V T) are a promising alternative in the implementation of low power electronics. The implementation of gain-cell embedded DRAMs (eDRAMs) based on FinFET devices requires a careful design to ... -
Reliability study on technology trends beyond 20nm
Amat Bertran, Esteve; Calomarde Palomino, Antonio; Rubio Sola, Jose Antonio (Lodz University of Technology, 2013)
Text en actes de congrés
Accés restringit per política de l'editorialIn this work, an assessment of different technology trends (planar CMOS, FinFET and III-V MOSFETs) has been carried out in front of some different reliability scenarios (variability and soft errors). The logic circuits ... -
Review on suitable eDRAM configurations for next nano-metric electronics era
Amat, Esteve; Canal Corretger, Ramon; Calomarde Palomino, Antonio; Rubio Sola, Jose Antonio (2018-03)
Article
Accés obertWe summarize most of our studies focused on the main reliability issues that can threat the gain-cells eDRAM behavior when it is simulated at the nano-metric device range has been collected in this review. So, to outperform ... -
Robust sequential circuits design technique for low voltage and high noise scenarios
García Leyva, Lancelot; Rivera Dueñas, Juan; Calomarde Palomino, Antonio; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio (2016)
Text en actes de congrés
Accés obertAll electronic processing components in future deep nanotechnologies will exhibit high noise level and/ or low S/N ratios because of the extreme voltage reduction and the nearly erratic nature of such devices. ... -
SET and noise fault tolerant circuit design techniques: application to 7 nm FinFET
Calomarde Palomino, Antonio; Amat Bertran, Esteve; Moll Echeto, Francisco de Borja; Vigara Campmany, Julio Enrique; Rubio Sola, Jose Antonio (2014-04-01)
Article
Accés obertIn the near future of high component density and low-power technologies, soft errors occurring not only in memory systems and latches but also in the combinational parts of logic circuits will seriously affect the reliable ... -
Suitability of FinFET introduction into eDRAM cells for operate at sub-threshold level
Amat, Esteve; Calomarde Palomino, Antonio; Canal Corretger, Ramon; Rubio Sola, Jose Antonio (Institute of Electrical and Electronics Engineers (IEEE), 2017)
Comunicació de congrés
Accés restringit per política de l'editorialThis paper explores the feasibility, in terms of performance and reliability, of gain-cell embedded DRAM (eDRAM) to be operative at sub-threshold range, when they are implemented with 10 nm FinFET devices. The use of ... -
Turtle Logic: A new probabilistic design methodology of nanoscale digital circuits
García Leyva, Lancelot; Calomarde Palomino, Antonio; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio (IEEE Press. Institute of Electrical and Electronics Engineers, 2010)
Text en actes de congrés
Accés obertAs devices and operating voltages are scaled down, future circuits will be plagued by higher soft error rates, reduced noise margins and defective devices. A key challenge for the future technologies is to retain circuit ... -
Turtle logic: Novel IC digital probabilistic design methodology
García Leyva, Lancelot; Rubio Sola, Jose Antonio; Moll Echeto, Francisco de Borja; Calomarde Palomino, Antonio (2010)
Text en actes de congrés
Accés obertFuture electronic devices are expected to operate at lower voltage supply to save power, especially in ultimate and new technologies. The resulting reduction of logic levels approaches the thermal noise limit, and ... -
Two examples of approximate arithmetic to reduce hardware complexity and power consumption
Fornt Mas, Jordi; Jin, Leixin; Etxezarreta, Imanol; Fontova, Pau; Altet Sanahujes, Josep; Calomarde Palomino, Antonio; Morancho Llena, Enrique; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio (Institute of Electrical and Electronics Engineers (IEEE), 2022)
Comunicació de congrés
Accés obertAs the end of Moore's Law approaches, electronic system designers must find ways to keep up with the ever increasing computational demands of the modern era. Some computationally intensive applications, such as multimedia ... -
Variability impact on on-chip memory data paths
Amat Bertran, Esteve; Calomarde Palomino, Antonio; Canal Corretger, Ramon; Rubio Sola, Jose Antonio (2014)
Comunicació de congrés
Accés obertProcess variations have a large impact on device and circuit reliability and performance. Few studies are focused on their impact on more complex systems, as for example their influence in a data path. In our study, the ... -
Variation tolerant self-adaptive clock generation architecture based on a ring oscillator
Pérez Puigdemont, Jordi; Calomarde Palomino, Antonio; Moll Echeto, Francisco de Borja (Institute of Electrical and Electronics Engineers (IEEE), 2012)
Comunicació de congrés
Accés obertIn this work we propose a self-adaptive clock based on a ring oscillator as the solution for the increasing uncertainty in the critical path delay. This increase in uncertainty forces to add more safety margins to the ...