Exploració per autor "Calomarde Palomino, Antonio"Més informacióMés informació

Ara es mostren els items 19-38 de 44

    • Eines d’autor: avaluació de noves eines orientades al desenvolupament de competències genèriques per la millora del procés d’aprenentatge autònom dels estudiants 

      Calomarde Palomino, Antonio; Rubio Sola, Jose Antonio; Vigara Campmany, Julio Enrique; Romeral Martínez, José Luis; Ortega Redondo, Juan Antonio (Universitat Politècnica de Catalunya. Institut de Ciències de l'Educació, 2013-02-08)
      Text en actes de congrés / Comunicació de congrés
      Accés obert
      Els cursos on-line massius (Massive Open On-line Courses) estan emergent i suposarà un gran repte en l’educació universitària en els propers anys. Universitats com Standford i MIT han començat aquest any cursos en obert ...

    • ELECTRÒNICA DIGITAL (2n quadrimestre, examen parcial) - B 

      Calomarde Palomino, Antonio (Universitat Politècnica de Catalunya, 2010-04-09)
      Examen
      Accés restringit a la comunitat UPC

    • ELECTRÒNICA DIGITAL (Examen 2n Quadr.) 

      Calomarde Palomino, Antonio (Universitat Politècnica de Catalunya, 2008-04-11)
      Examen
      Accés restringit a la comunitat UPC

    • ETS 2022 ORGANIZING COMMITTEE 

      Manich Bou, Salvador; Rodríguez Montañés, Rosa; Bernardi, Paolo; Tille, Daniel; Mir, Salvador; Bosio, Alberto; Arumi Delgado, Daniel; Gómez Pau, Álvaro; Cassano, Luca; Jiao, Hailong; Miclea, Liviu; Sanchez, Ernesto; Savino, Alessandro; Canal Corretger, Ramon; Eggersglüß, Stephan; Fransi, Sergi; Taouil, Mottaqiallah; Calomarde Palomino, Antonio; Weiner, Michael; Michael, Maria K.; Sonza Reorda, Matteo; Larsson, Erik; Vatajelu, Elena-Ioana; Stratigopoulos, Haralampos-G.; Parisi Baradad, Vicenç; Jiao, Hailong; Huang, Junlin; Li, Huawei; Chillarige, Sameer; Kameyama, Shuichi; Carro, Luigi; Su, Fei; Nicolici, Nicola; Huang, Shi-Yu (2022-05)
      Text en actes de congrés
      Accés obert

    • FinFET and III-V/Ge technology impact on 3T1D cell behavior 

      Amat Bertran, Esteve; Calomarde Palomino, Antonio; Almudever, Carmen G.; Aymerich Capdevila, Nivard; Canal Corretger, Ramon; Rubio Sola, Jose Antonio (2013)
      Comunicació de congrés
      Accés obert
      In this work, we assess the performance of a ring oscillator and a DRAM cell when they are implemented with different technologies (planar CMOS, FinFET and III-V MOSFETs), and subjected to different reliability ...

    • Fundamentos de electrónica 

      Calomarde Palomino, Antonio (Edicions UPC, 2002)
      Llibre
      Accés restringit a la comunitat UPC
      En este libro se recogen los conceptos necesarios para cubrir un curso completo de Electrónica. Se empieza con una descripción de los dispositivos fundamentales utilizados en Electrónica (Diodos, transistor bipolar, ...

    • High level spectral-based análisis of power concumption in DSP's systems 

      Calomarde Palomino, Antonio; Mateo Peña, Diego; Rubio Sola, Jose Antonio (Institute of Electrical and Electronics Engineers (IEEE), 2006)
      Text en actes de congrés
      Accés restringit per política de l'editorial
      In this paper, an efficient technique to evaluate temporal correlation and transition activity at high level in DSP systems is presented. The method is based on the spectral distribution of signals and has the advantage ...

    • Impact of finfet and III-V/Ge technology on logic and memory cell behavior 

      Amat Bertran, Esteve; Calomarde Palomino, Antonio; García Almudéver, Carmen; Aymerich Capdevila, Nivard; Canal Corretger, Ramon; Rubio Sola, Jose Antonio (2013-11-20)
      Article
      Accés restringit per política de l'editorial
      In this work, we assess the performance of a ring oscillator and a DRAM cell when they are implemented with different technologies (planar CMOS, FinFET and III-V MOSFETs), and subjected to different reliability scenarios ...

    • IMPLEMENTACIÓ DE SISTEMES AUDIOVISUALS (Examen 2n quadrimestre, 1r parcial) 

      Calomarde Palomino, Antonio (Universitat Politècnica de Catalunya, 2013-04-18)
      Examen
      Accés restringit a la comunitat UPC

    • IMPLEMENTACIÓ DE SISTEMES AUDIOVISUALS (Examen 2n quadrimestre, 2n parcial) 

      Calomarde Palomino, Antonio (Universitat Politècnica de Catalunya, 2013-06-10)
      Examen
      Accés restringit a la comunitat UPC

    • IMPLEMENTACIÓ DE SISTEMES AUDIOVISUALS (Examen 2n quadrimestre, 2n parcial) 

      Calomarde Palomino, Antonio (Universitat Politècnica de Catalunya, 2012-06-18)
      Examen
      Accés restringit a la comunitat UPC

    • Influence of punch trough stop layer and well depths on the robustness of bulk FinFETs to heavy ions impact 

      Calomarde Palomino, Antonio; Manich Bou, Salvador; Rubio Sola, Jose Antonio; Gamiz, Francisco (Institute of Electrical and Electronics Engineers (IEEE), 2022-05-02)
      Article
      Accés obert
      This study analyzes the effects of the punch-through stop (PTS) layer and well depth in a bulk FinFET SRAM cell on the fraction of charge generated by an ion impact that is collected by the FinFET channel. More than 1700 ...

    • Introducing autonomous vehicles into an unergraduate engineering course 

      Blesa Izquierdo, Joaquim; Ponsa Asensio, Pere; Calomarde Palomino, Antonio; García Abián, Jonathan; Repecho del Corral, Víctor (Universitat Politècnica de Catalunya, 2022-09)
      Text en actes de congrés
      Accés obert
      Autonomous vehicles (AVs) are of great interest for the automotive industry and are expected to revolutionize mobility and public transportation. The university can contribute to the design and development of autonomous ...

    • New redundant logic design concept for high noise and low voltage scenarios 

      García Leyva, Lancelot; Andrade Miceli, Dennis Michael; Gómez Fernández, Sergio; Calomarde Palomino, Antonio; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio (2011-12)
      Article
      Accés restringit per política de l'editorial
      This paper presents a new redundant logia design concept named Turtle Logic(TL).It is a new probabilistic logic method based on port redundancy and complementary data, oriented toward emerging technologies beyond CMOS, ...

    • Novel redundant logic design for noisy low voltage scenarios 

      García Leyva, Lancelot; Calomarde Palomino, Antonio; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio (2013)
      Text en actes de congrés
      Accés restringit per política de l'editorial
      The concept worked in this paper named Turtle Logic (TL) is a probabilistic logic method based on port redundancy and complementary data, oriented to emerging CMOS technologies and beyond, where the thermal noise could be ...

    • Optimization of FinFET-based gain cells for low power sub-vt embedded drams 

      Amat, Esteve; Calomarde Palomino, Antonio; Canal Corretger, Ramon; Rubio Sola, Jose Antonio (2018-06-01)
      Article
      Accés obert
      Sub-threshold circuits (sub-V T) are a promising alternative in the implementation of low power electronics. The implementation of gain-cell embedded DRAMs (eDRAMs) based on FinFET devices requires a careful design to ...

    • Reliability study on technology trends beyond 20nm 

      Amat Bertran, Esteve; Calomarde Palomino, Antonio; Rubio Sola, Jose Antonio (Lodz University of Technology, 2013)
      Text en actes de congrés
      Accés restringit per política de l'editorial
      In this work, an assessment of different technology trends (planar CMOS, FinFET and III-V MOSFETs) has been carried out in front of some different reliability scenarios (variability and soft errors). The logic circuits ...

    • Review on suitable eDRAM configurations for next nano-metric electronics era 

      Amat, Esteve; Canal Corretger, Ramon; Calomarde Palomino, Antonio; Rubio Sola, Jose Antonio (2018-03)
      Article
      Accés obert
      We summarize most of our studies focused on the main reliability issues that can threat the gain-cells eDRAM behavior when it is simulated at the nano-metric device range has been collected in this review. So, to outperform ...

    • Robust sequential circuits design technique for low voltage and high noise scenarios 

      García Leyva, Lancelot; Rivera Dueñas, Juan; Calomarde Palomino, Antonio; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio (2016)
      Text en actes de congrés
      Accés obert
      All electronic processing components in future deep nanotechnologies will exhibit high noise level and/ or low S/N ratios because of the extreme voltage reduction and the nearly erratic nature of such devices. ...

    • SET and noise fault tolerant circuit design techniques: application to 7 nm FinFET 

      Calomarde Palomino, Antonio; Amat Bertran, Esteve; Moll Echeto, Francisco de Borja; Vigara Campmany, Julio Enrique; Rubio Sola, Jose Antonio (2014-04-01)
      Article
      Accés obert
      In the near future of high component density and low-power technologies, soft errors occurring not only in memory systems and latches but also in the combinational parts of logic circuits will seriously affect the reliable ...