Exploració per autor "González Colás, Antonio María"
Ara es mostren els items 225-237 de 237
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Value prediction for speculative multithreaded architectures
Marcuello Pascual, Pedro; Tubella Murgadas, Jordi; González Colás, Antonio María (Institute of Electrical and Electronics Engineers (IEEE), 1999)
Text en actes de congrés
Accés obertThe speculative multithreading paradigm (speculative thread-level parallelism) is based on the concurrent execution of control-speculative threads. The efficiency of microarchitectures that adopt this paradigm strongly ... -
Variable-based multi-module data caches for clustered VLIW processors
Gibert Codina, Enric; Abella Ferrer, Jaume; Sánchez Navarro, Jesús; Vera Rivera, Francisco Javier; González Colás, Antonio María (Institute of Electrical and Electronics Engineers (IEEE), 2005)
Text en actes de congrés
Accés obertMemory structures consume an important fraction of the total processor energy. One solution to reduce the energy consumed by cache memories consists of reducing their supply voltage and/or increase their threshold voltage ... -
VCTA: A Via-Configurable Transistor Array regular fabric
Pons Solé, Marc; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio; Abella Ferrer, Jaume; Vera Rivera, Francisco Javier; González Colás, Antonio María (IEEE Computer Society Publications, 2010)
Text en actes de congrés
Accés obertLayout regularity is introduced progressively by integrated circuit manufacturers to reduce the increasing systematic process variations in the deep sub-micron era. In this paper we focus on a scenario where layout regularity ... -
Very low power pipelines using significance compression
Canal Corretger, Ramon; González Colás, Antonio María; Smith, James E. (Institute of Electrical and Electronics Engineers (IEEE), 2000)
Text en actes de congrés
Accés obertData, addresses, and instructions are compressed by maintaining only significant bytes with two or three extension bits appended to indicate the significant byte positions. This significance compression method is integrated ... -
Via-configurable transistors array: a regular design technique to improve ICs yield
Pons, Marc; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio; Abella Ferrer, Jaume; Vera Rivera, Francisco Javier; González Colás, Antonio María (Institute of Electrical and Electronics Engineers (IEEE), 2007)
Text en actes de congrés
Accés obertProcess variations are a major bottleneck for digital CMOS integrated circuits manufacturability and yield. That is why regular techniques with different degrees of regularity are emerging as possible solutions. Our ... -
Virtual cluster scheduling through the scheduling graph
Codina Viñas, Josep M.; Sánchez Navarro, Jesús; González Colás, Antonio María (Institute of Electrical and Electronics Engineers (IEEE), 2007)
Text en actes de congrés
Accés obertThis paper presents an instruction scheduling and cluster assignment approach for clustered processors. The proposed technique makes use of a novel representation named the scheduling graph which describes all possible ... -
Virtual registers
González Colás, Antonio María; Valero Cortés, Mateo; González González, José; Monreal Arnal, Teresa (Institute of Electrical and Electronics Engineers (IEEE), 1997)
Text en actes de congrés
Accés obertThe number of physical registers is one of the critical issues of current superscalar out-of-order processors. Conventional architectures allocate, in the decoding stage, a new storage location (e.g. a physical register) ... -
Virtual-physical registers
González Colás, Antonio María; González González, José; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 1998)
Text en actes de congrés
Accés obertA novel dynamic register renaming approach is proposed in this work. The key idea of the novel scheme is to delay the allocation of physical registers until a late stage in the pipeline, instead of doing it in the decode ... -
Visibility rendering order: Improving energy efficiency on mobile GPUs through frame coherence
Lucas Casamayor, Enrique de; Marcuello Pascual, Pedro; Parcerisa Bundó, Joan Manuel; González Colás, Antonio María (2019-02-01)
Article
Accés obertDuring real-time graphics rendering, objects are processed by the GPU in the order they are submitted by the CPU, and occluded surfaces are often processed even though they will end up not being part of the final image, ... -
vPROBE: Variation aware post-silicon power/performance binning using embedded 3T1D cells
Ganapathy, Shrikanth; Canal Corretger, Ramon; González Colás, Antonio María; Rubio Sola, Jose Antonio (2010-09-05)
Report de recerca
Accés obertIn this paper, we present an on-die post-silicon binning methodology that takes into account the effect of static and dynamic variations and categorizes every processor based on power/performance.The proposed scheme is ... -
Warm-up simulation methodology for HW/SW co-designed processors
Brankovic, Aleksandar; Stavrou, K.; Gibert Codina, Enric; González Colás, Antonio María (ACM, 2014)
Text en actes de congrés
Accés restringit per política de l'editorialEvaluation techniques in microprocessor design are mostly based on simulating selected application samples using a cycle-accurate simulator. In order to achieve accurate results, microarchitectural structures are warmed-up ... -
XFeatur: Hardware feature extraction for DNN auto-tuning
Sierra Acosta, Jorge; Diavastos, Andreas; González Colás, Antonio María (Institute of Electrical and Electronics Engineers (IEEE), 2022)
Text en actes de congrés
Accés obertIn this work, we extend the auto-tuning process of the state-of-the-art TVM framework with XFeatur; a tool that extracts new meaningful hardware-related features that improve the quality of the representation of the search ... -
δLTA:: Decoupling camera sampling from processing to avoid redundant computations in the vision pipeline
Taranco Serna, Raúl; Arnau Montañés, José María; González Colás, Antonio María (Association for Computing Machinery (ACM), 2023)
Text en actes de congrés
Accés obertContinuous Vision (CV) systems are essential for emerging applications like Autonomous Driving (AD) and Augmented/Virtual Reality (AR/VR). A standard CV System-on-a-Chip (SoC) pipeline includes a frontend for image capture ...