Exploració per autor "González Colás, Antonio María"
Ara es mostren els items 201-220 de 237
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TCOR: a tile cache with optimal replacement
(Institute of Electrical and Electronics Engineers (IEEE), 2022)
Text en actes de congrés
Accés obertCache Replacement Policies are known to have an important impact on hit rates. The OPT replacement policy [27] has been formally proven as optimal for minimizing misses. Due to its need to look far ahead for future memory ... -
Tendencias en la microarquitectura de los procesadores
(Asociación de Técnicos de Informática, 2000-05)
Article
Accés obertEn este artículo se revisa la microarquitectura de los procesadores actuales. Seguidamente de presentan las principales expectativas en la evolución de la tecnología. A continuación de destacan las principales limitaciones ... -
The Auction: optimizing banks usage in non-uniform cache architectures
(Association for Computing Machinery (ACM), 2010)
Text en actes de congrés
Accés restringit per política de l'editorialThe growing influence of wire delay in cache design has meant that access latencies to last-level cache banks are no longer constant. Non-Uniform Cache Architectures (NUCAs)have been proposed to address this problem. ... -
The dark side of DNN pruning
(Institute of Electrical and Electronics Engineers (IEEE), 2018)
Text en actes de congrés
Accés restringit per política de l'editorialDNN pruning has been recently proposed as an effective technique to improve the energy-efficiency of DNN-based solutions. It is claimed that by removing unimportant or redundant connections, the pruned DNN delivers higher ... -
The design and performance of a conflict-avoiding cache
(Institute of Electrical and Electronics Engineers (IEEE), 1997)
Text en actes de congrés
Accés obertHigh performance architectures depend heavily on efficient multi-level memory hierarchies to minimize the cost of accessing data. This dependence will increase with the expected increases in relative distance to main memory. ... -
The effectiveness of loop unrolling for modulo scheduling in clustered VLIW architectures
(Institute of Electrical and Electronics Engineers (IEEE), 2000)
Text en actes de congrés
Accés obertClustered organizations are becoming a common trend in the design of VLIW architectures. In this work we propose a novel modulo scheduling approach for such architectures. The proposed technique performs the cluster ... -
The latency hiding effectiveness of decoupled access/execute processors
(Institute of Electrical and Electronics Engineers (IEEE), 1998)
Text en actes de congrés
Accés obertSeveral studies have demonstrated that out-of-order execution processors may not be the most adequate organization for wide-issue processors due to the increasing penalties that wire delays cause in the issue logic. The ... -
The migration prefetcher: anticipating data promotion in dynamic NUCA caches
(2012-01)
Article
Accés obert -
The synergy of multithreading and access/execute decoupling
(Institute of Electrical and Electronics Engineers (IEEE), 1999)
Text en actes de congrés
Accés obertThis work presents and evaluates a novel processor microarchitecture which combines two paradigms: access/execute decoupling and simultaneous multithreading. We investigate how both techniques complement each other: while ... -
The Xor embedding: An embedding of hypercubes onto rings and toruses
(Institute of Electrical and Electronics Engineers (IEEE), 1993)
Text en actes de congrés
Accés obertMany parallel algorithms use hypercubes as the communication topology among processes, which make them suitable to be executed on a hypercube multicomputer. In this way the communication cost is kept to a minimum since ... -
Thermal-aware clustered microarchitectures
(Institute of Electrical and Electronics Engineers (IEEE), 2004)
Text en actes de congrés
Accés obertAs frequencies and feature size scale faster than operating voltages, power density is increasing in each processor generation. Power density and the cost of removing the heat it generates are increasing at the same rate. ... -
Thread partitioning and value prediction for exploiting speculative thread-level parallelism
(2004-02)
Article
Accés obertSpeculative thread-level parallelism has been recently proposed as a source of parallelism to improve the performance in applications where parallel threads are hard to find. However, the efficiency of this execution model ... -
Thread-spawning schemes for speculative multithreading
(IEEE Computer Society, 2002)
Text en actes de congrés
Accés obertSpeculative multithreading has been recently proposed to boost performance by means of exploiting thread-level parallelism in applications difficult to parallelize. The performance of these processors heavily depends on ... -
Trace-level reuse
(Institute of Electrical and Electronics Engineers (IEEE), 1999)
Text en actes de congrés
Accés obertTrace-level reuse is based on the observation that some traces (dynamic sequences of instructions) are frequently repeated during the execution of a program, and in many cases, the instructions that make up such traces ... -
Trace-level speculative multithreaded architecture
(Institute of Electrical and Electronics Engineers (IEEE), 2002)
Text en actes de congrés
Accés obertThis paper presents a novel microarchitecture to exploit trace-level speculation by means of two threads working cooperatively in a speculative and non-speculative way respectively. The architecture presents two main ... -
TRAMS Project: variability and reliability of SRAM memories in sub-22nm bulk-CMOS technologies
(Elsevier, 2011-12-22)
Article
Accés restringit per política de l'editorialThe TRAMS (Terascale Reliable Adaptive MEMORY Systems) project addresses in an evolutionary way the ultimate CMOS scaling technologies and paves the way for revolutionary, most promising beyond-CMOS technologies. In this ... -
Trends in processor architecture
(Springer, 2019-01-01)
Capítol de llibre
Accés obertThis chapter presents an overview of the main trends in processor architecture. It starts with an analysis of the past evolution of processors and the main driving forces behind it, and then it focuses on a description of ... -
Triangle Dropping: An occluded-geometry predictor for energy-efficient mobile GPUs
(Association for Computing Machinery (ACM), 2022-09)
Article
Accés obertThis article proposes a novel micro-architecture approach for mobile GPUs aimed at early removing the occluded geometry in a scene by leveraging frame-to-frame coherence, thus reducing the overall energy consumption. Mobile ... -
Ultra-low power render based collision detection for CPU/GPU systems
(Association for Computing Machinery (ACM), 2015)
Text en actes de congrés
Accés restringit per política de l'editorialSmartphones have become powerful computing systems able to carry out complex tasks, such as web browsing, image processing and gaming, among others. Graphics animation applications such as 3D games represent a large ... -
Understanding the thermal implications of multicore architectures
(2007-08)
Article
Accés obertMulticore architectures are becoming the main design paradigm for current and future processors. The main reason is that multicore designs provide an effective way of overcoming instruction-level parallelism (ILP) limitations ...
