Exploració per autor "González Colás, Antonio María"
Ara es mostren els items 152-171 de 237
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Omega-Test: A predictive early-Z culling to improve the graphics pipeline energy-efficiency
(2022-12-01)
Article
Accés obertThe most common task of GPUs is to render images in real time. When rendering a 3D scene, a key step is to determine which parts of every object are visible in the final image. There are different approaches to solve the ... -
On reducing register pressure and energy in multiple-banked register files
(Institute of Electrical and Electronics Engineers (IEEE), 2003)
Text en actes de congrés
Accés obertThe storage for speculative values in superscalar processors is one of the main sources of complexity and power dissipation. We present a novel technique to reduce register requirements as well as their dynamic and static ... -
On the effectiveness of hybrid mechanisms on reduction of parametric failures in caches
(2011-12-05)
Report de recerca
Accés restringit per política de l'editorialIn this paper, we provide an insight on the different proactive read/write assist methods (wordline boosting & adaptive body biasing) that help in preventing (and reducing) parametric failures when coupled with reactive ... -
On-chip interconnects and instruction steering schemes for clustered microarchitectures
(2005-02)
Article
Accés obertClustering is an effective microarchitectural technique for reducing the impact of wire delays, the complexity, and the power requirements of microprocessors. In this work, we investigate the design of on-chip interconnection ... -
On-line failure detection and confinement in caches
(Institute of Electrical and Electronics Engineers (IEEE), 2008)
Text en actes de congrés
Accés obertTechnology scaling leads to burn-in phase out and increasing post-silicon test complexity, which increases in-the-field error rate due to both latent defects and actual errors. As a consequence, there is an increasing need ... -
Online error detection and correction of erratic bits in register files
(2009-06)
Text en actes de congrés
Accés obertAggressive voltage scaling needed for low power in each new process generation causes large deviations in the threshold voltage of minimally sized devices of the 6T SRAM cell. Gate oxide scaling can cause large transient ... -
Optimizing program locality through CMEs and GAs
(Institute of Electrical and Electronics Engineers (IEEE), 2003)
Text en actes de congrés
Accés obertCaches have become increasingly important with the widening gap between main memory and processor speeds. Small and fast cache memories are designed to bridge this discrepancy. However, they are only effective when programs ... -
P-slice based efficient speculative multithreading
(IEEE Computer Society Publications, 2009-12-16)
Text en actes de congrés
Accés obertMicroprocessor industry has recently shifted towards multi-core to take advantage of the ever increasing number of transistors provided by the new technologies. Unfortunately, the multi-core approach does not allow single ... -
PARSAR: A SAR processor implemented in a cluster of workstations
(ESA Publications Division, 1997)
Text en actes de congrés
Accés obertA parallel SAR processor is presented in this paper. The target configuration is a cluster of UNIX workstations, available in most user sites. This fact allows to obtain an increased computing performance without the need ... -
PARSAR: Parallelisation of a chirp scaling algorithm SAR processor
(Ch. Lengauer, M. Grielb, S. Gorlatch. BERLIN, NEW YORK, Springer-Verlag Cop.1997, 1997)
Text en actes de congrés
Accés obertA parallel SAR processor is presented in this paper. The target configuration is a cluster of UNIX workstations, available in most user sites. This fact allows to obtain an increased computing performance without the need ... -
Parsar: parallelisation of a chirp scaling algorithm sar processor
(1997-08)
Article
Accés restringit per política de l'editorialA parallel SAR processor is presented in this paper. The target configuration is a cluster of UNIX workstations, available in most user sites. This fact allows to obtain an increased computing performance without the need ... -
Penelope: The NBTI-aware processor
(IEEE Computer Society, 2007)
Text en actes de congrés
Accés obertTransistors consist of lower number of atoms with every technology generation. Such atoms may be displaced due to the stress caused by high temperature, frequency and current, leading to failures. NBTI (negative bias ... -
Performance analysis and optimization of automatic speech recognition
(2018-10-01)
Article
Accés obertFast and accurate Automatic Speech Recognition (ASR) is emerging as a key application for mobile devices. Delivering ASR on such devices is challenging due to the compute-intensive nature of the problem and the power ... -
Performance analysis of non-uniform cache architecture policies for chip-multiprocessors using the Parsec v2.0 Benchmark Suite
(2009-09)
Text en actes de congrés
Accés restringit per política de l'editorialNon-Uniform Cache Architectures (NUCA)have been proposed as a solution to overcome wire delays that will dominate on-chip latencies in Chip Multiprocessor designs in the near future. This novel means of organization divides ... -
Power efficient data cache designs
(Institute of Electrical and Electronics Engineers (IEEE), 2003)
Text en actes de congrés
Accés obertWe investigate some power efficient data cache designs that try to significantly reduce the cache energy consumption, both static and dynamic, with a minimal impact in performance. The basic idea is to combine different ... -
Power- and complexity-aware issue queue designs
(2003-09)
Article
Accés obertThe improved performance of current microprocessors brings with it increasingly complex and power-dissipating issue logic. Recent proposals introduce a range of mechanisms for tackling this problem. -
Power-aware control speculation through selective throttling
(Institute of Electrical and Electronics Engineers (IEEE), 2003)
Text en actes de congrés
Accés obertWith the constant advances in technology that lead to the increasing of the transistor count and processor frequency, power dissipation is becoming one of the major issues in high-performance processors. These processors ... -
Power/performance/thermal design-space exploration for multicore architectures
(2008-05)
Article
Accés obertMulticore architectures have been ruling the recent microprocessor design trend. This is due to different reasons: better performance, thread-level parallelism bounds in modern applications, ILP diminishing returns, better ... -
QeiHaN: An energy-efficient DNN accelerator that leverages log quantization in NDP architectures
(Institute of Electrical and Electronics Engineers (IEEE), 2023)
Comunicació de congrés
Accés obertThe constant growth of DNNs makes them challenging to implement and run efficiently on traditional computecentric architectures. Some works have attempted to enhance accelerators by adding more compute units and on-chip ... -
Quantitative characterization of the software layer of a HW/SW co-designed processor
(Institute of Electrical and Electronics Engineers (IEEE), 2016)
Text en actes de congrés
Accés obertHW/SW co-designed processors currently have a renewed interest due to their capability to boost performance without running into the power and complexity walls. By employing a software layer that performs dynamic binary ...
