Exploració per autor "González Colás, Antonio María"
Ara es mostren els items 127-146 de 237
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Last Bank: dealing with address reuse in non-uniform cache architecture for CMPs
(2009-01-16)
Report de recerca
Accés obertIn response to the constant increase in wire delays, Non-Uniform Cache Architecture (NUCA) has been introduced as an effective memory model for dealing with growing memory latencies. This architecture divides a large memory ... -
Late allocation and early release of physical registers
(2004-10)
Article
Accés obertThe register file is one of the critical components of current processors in terms of access time and power consumption. Among other things, the potential to exploit instruction-level parallelism is closely related to the ... -
LAWS: Locality-AWare Scheme for automatic speech recognition
(Institute of Electrical and Electronics Engineers (IEEE), 2020-08-01)
Article
Accés obertAutomatic Speech Recognition (ASR) systems are changing the way people interact with different applications on mobile devices. Fulfilling such user-interactivity requires not only a highly accurate, large-vocabulary ... -
Leveraging register windows to reduce physical registers to the bare minimum
(2010-12)
Article
Accés obertRegister window is an architectural technique that reduces memory operations required to save and restore registers across procedure calls. Its effectiveness depends on the size of the register file. Such register requirements ... -
Leveraging run-time feedback for efficient ASR acceleration
(Institute of Electrical and Electronics Engineers (IEEE), 2019)
Text en actes de congrés
Accés obertIn this work, we propose Locality-AWare-Scheme (LAWS) for an Automatic Speech Recognition (ASR) accelerator in order to significantly reduce its energy consumption and memory requirements, by leveraging the locality among ... -
Lifetime-sensitive modulo scheduling in a production environment
(2001-03)
Article
Accés obertThis paper presents a novel software pipelining approach, which is called Swing Modulo Scheduling (SMS). It generates schedules that are near optimal in terms of initiation interval, register requirements, and stage count. ... -
Lightweight register file caching in collector units for GPUs
(Association for Computing Machinery (ACM), 2023)
Text en actes de congrés
Accés obertModern GPUs benefit from a sizable Register File (RF) to provide fine-grained thread switching. As the RF is huge and accessed frequently, it consumes a considerable share of the dynamic energy of the GPU. Designing a ... -
Local scheduling techniques for memory coherence in a clustered VLIW processor with a distributed data cache
(Institute of Electrical and Electronics Engineers (IEEE), 2003)
Text en actes de congrés
Accés obertClustering is a common technique to deal with wire delays. Fully-distributed architectures, where the register file, the functional units and the cache memory are partitioned, are particularly effective to deal with these ... -
LOCATOR: Low-power ORB accelerator for autonomous cars
(Elsevier, 2023-04)
Article
Accés obertSimultaneous Localization And Mapping (SLAM) is crucial for autonomous navigation. ORB-SLAM is a state-of-the-art Visual SLAM system based on cameras used for self-driving cars. In this paper, we propose a high-performance, ... -
Low Vccmin fault-tolerant cache with highly predictable performance
(IEEE Press. Institute of Electrical and Electronics Engineers, 2009)
Text en actes de congrés
Accés restringit per política de l'editorialTransistors per area unit double in every new technology node. However, the electric field density and power demand grow if Vcc is not scaled. Therefore, Vcc must be scaled in pace with new technology nodes to prevent ... -
Low-complexity distributed issue queue
(IEEE Computer Society, 2004)
Text en actes de congrés
Accés obertAs technology evolves, power density significantly increases and cooling systems become more complex and expensive. The issue logic is one of the processor hotspots and, at the same time, its latency is crucial for the ... -
Low-power automatic speech recognition through a mobile GPU and a Viterbi accelerator
(2017-04-12)
Article
Accés obertAutomatic speech recognition (ASR) has become a core technology for mobile devices. Delivering real-time and accurate ASR has a huge computational cost, which is challenging to achieve in tightly energy-constrained platforms ... -
LRU-PEA: A smart replacement policy for non-uniform cache architectures on chip multiprocessors
(2009-05-14)
Report de recerca
Accés obertThe increasing speed-gap between processor and memory and the limited memory bandwidth make last-level cache performance crucial for CMP architectures. Non Uniform Cache Architectures (NUCA) has been introduced to deal ... -
LRU-PEA: A smart replacement policy for non-uniform cache architectures on chip multiprocessors
(Institute of Electrical and Electronics Engineers (IEEE), 2009)
Text en actes de congrés
Accés obertThe increasing speed-gap between processor and memory and the limited memory bandwidth make last-level cache performance crucial for CMP architectures. non uniform cache architectures (NUCA) have been introduced to deal ... -
MASkIt: soft error rate estimation for combinatorial circuits
(Institute of Electrical and Electronics Engineers (IEEE), 2016)
Text en actes de congrés
Accés restringit per política de l'editorialIntegrated circuits are getting increasingly vulnerable to soft errors; as a consequence, soft error rate (SER) estimation has become an important and very challenging goal. In this work, a novel approach for SER estimation ... -
MEGsim: A Novel methodology for efficient simulation of graphics workloads in GPUs
(Institute of Electrical and Electronics Engineers (IEEE), 2022)
Text en actes de congrés
Accés obertAn important drawback of cycle-accurate microarchitectural simulators is that they are several orders of magnitude slower than the system they model. This becomes an important issue when simulations have to be repeated ... -
Memory bank predictors
(Institute of Electrical and Electronics Engineers (IEEE), 2005)
Text en actes de congrés
Accés obertCache memories are commonly implemented through multiple memory banks to improve bandwidth and latency. The early knowledge of the data cache bank that an instruction will access can help to improve the performance in ... -
MeRLiN: Exploiting dynamic instruction behavior for fast and accurate microarchitecture level reliability assessment
(Association for Computing Machinery (ACM), 2017)
Text en actes de congrés
Accés obertEarly reliability assessment of hardware structures using microarchitecture level simulators can effectively guide major error protection decisions in microprocessor design. Statistical fault injection on microarchitectural ... -
Mitosis: A speculative multithreaded processor based on pre-computation slices
(2008-07)
Article
Accés obertThis paper presents the Mitosis framework, which is a combined hardware-software approach to speculative multithreading, even in the presence of frequent dependences among threads. Speculative multithreading increases ... -
MODEST: a model for energy estimation under spatio-temporal variability
(Institute of Electrical and Electronics Engineers (IEEE), 2010)
Text en actes de congrés
Accés restringit per política de l'editorialEstimation of static and dynamic energy of caches is critical for high-performance low-power designs. Commercial CAD tools performing energy estimation statically are not aware of the changing operating and environmental ...
