Exploració per autor "González Colás, Antonio María"
Ara es mostren els items 108-127 de 237
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Impact of parameter variations on circuits and microarchitecture
(2006-12)
Article
Accés obertParameter variations, which are increasing along with advances in process technologies, affect both timing and power. Variability must be considered at both the circuit and microarchitectural design levels to keep pace ... -
Impact of positive bias temperature instability (PBTI)
(2011)
Text en actes de congrés
Accés restringit per política de l'editorialMemory circuits are playing a key role in complex multicore systems with both data and instructions storage and mailbox communication functions. There is a general concern that conventional SRAM cell based on the 6T structure ... -
Implementing a hybrid SRAM / eDRAM NUCA architecture
(2010-08-27)
Report de recerca
Accés obertIn this paper, we propose a hybrid cache architecture that exploits the main features of both memory technologies, speed of SRAM and high density of eDRAM. We demonstrate, that due to the high locality found in emerging ... -
Implementing end-to-end register data-flow continuous self-test
(2011-08-01)
Article
Accés restringit per política de l'editorialWhile Moore's Law predicts the ability of semiconductor industry to engineer smaller and more efficient transistors and circuits, there are serious issues not contemplated in that law. One concern is the verification effort ... -
Improving branch prediction and predicated execution in out-of-order processors
(Institute of Electrical and Electronics Engineers (IEEE), 2007)
Text en actes de congrés
Accés obertIf-conversion is a compiler technique that reduces the misprediction penalties caused by hard-to-predict branches, transforming control dependencies into data dependencies. Although it is globally beneficial, it has a ... -
Improving latency tolerance of multithreading through decoupling
(2001-10)
Article
Accés obertThe increasing hardware complexity of dynamically scheduled superscalar processors may compromise the scalability of this organization to make an efficient use of future increases in transistor budget. SMT processors, ... -
Improving the energy efficiency of the graphics pipeline by reducing overshading
(2021)
Text en actes de congrés
Accés obertThe most common task of GPUs is to render images in real time. When rendering a 3D scene, a key step is determining which parts of every object are visible in the final image. There are different approaches to solve the ... -
Improving the performance efficiency of an IDS by exploiting temporal locality in network traffic
(2012)
Text en actes de congrés
Accés restringit per política de l'editorialNetwork traffic has traditionally exhibited temporal locality in the header field of packets. Such locality is intuitive and is a consequence of the semantics of network protocols. However, in contrast, the locality in the ... -
Improving the resilience of an IDS against performance throttling attacks
(Springer, 2012)
Text en actes de congrés
Accés restringit per política de l'editorialIntrusion Detection Systems (IDS) have emerged as one of the most promising ways to secure systems in the network. To be effective against evasion attempts, the IDS must provide tight bounds on performance. Otherwise an ... -
INFORMER: an integrated framework for early-stage memory robustness analysis
(European Interactive Digital Advertising Alliance (EDAA), 2014)
Text en actes de congrés
Accés restringit per política de l'editorialWith the growing importance of parametric (process and environmental) variations in advanced technologies, it has become a serious challenge to design reliable, fast and low-power embedded memories. Adopting a variation-aware ... -
Inherently workload-balanced clustered microarchitecture
(Institute of Electrical and Electronics Engineers (IEEE), 2005)
Text en actes de congrés
Accés obertThe performance of clustered microarchitectures relies on steering schemes that try to find the best trade-off between workload balance and inter-cluster communication penalties. In previously proposed clustered processors, ... -
Instruction replication for clustered microarchitectures
(Institute of Electrical and Electronics Engineers (IEEE), 2003)
Text en actes de congrés
Accés obertThis work presents a new compilation technique that uses instruction replication in order to reduce the number of communications executed on a clustered microarchitecture. For such architectures, the need to communicate ... -
Instruction scheduling for clustered VLIW architectures
(Institute of Electrical and Electronics Engineers (IEEE), 2000)
Text en actes de congrés
Accés obertClustered VLIW organizations are nowadays a common trend in the design of embedded/DSP processors. In this work we propose a novel modulo scheduling approach for such architectures. The proposed technique performs the ... -
iRMW: A low-cost technique to reduce NBTI-dependent parametric failures in L1 data caches
(Institute of Electrical and Electronics Engineers (IEEE), 2014)
Text en actes de congrés
Accés obertNegative bias temperature instability (NBTI) is a major cause of concern for chip designers because of its inherent ability to drastically reduce silicon reliability over the lifetime of the processor. Coupled with statistical ... -
Irregular accesses reorder unit: improving GPGPU memory coalescing for graph-based workloads
(2023-01)
Article
Accés obertGPGPU architectures have become the dominant platform for massively parallel workloads, delivering high performance and energy efficiency for popular applications such as machine learning, computer vision or self-driving ... -
Jacobi orderings for multi-port hypercubes
(Institute of Electrical and Electronics Engineers (IEEE), 1998)
Text en actes de congrés
Accés obertThe communication cost plays a key role in the performance of many parallel algorithms. In the particular case of the one-sided Jacobi method for symmetric eigenvalue and eigenvector computation the communication cost of ... -
Jacobi orderings for multi-port hypercubes.
(IEEE, 1998-03)
Text en actes de congrés
Accés obertThe communication cost plays a key role in the performance of many parallel algorithms. In the particular case of the one-sided Jacobi method for symmetric eigenvalue and eigenvector computation the communication cost of ... -
K-D Bonsai: ISA-extensions to compress K-D trees for autonomous driving tasks
(Association for Computing Machinery (ACM), 2023)
Text en actes de congrés
Accés obertAutonomous Driving (AD) systems extensively manipulate 3D point clouds for object detection and vehicle localization. Thereby, efficient processing of 3D point clouds is crucial in these systems. In this work we propose ... -
Keeping control transfer instructions out of the pipeline in architectures without condition codes
(1987-05)
Report de recerca
Accés obertThe execution of branch instructions involves a loss of performance in pipelined processors. In this paper we present a mechanism for executing this kind of instruction with a zero delay. This mechanism has been proposed ... -
Last Bank: dealing with address reuse in non-uniform cache architecture for CMPs
(2009-01-16)
Report de recerca
Accés obertIn response to the constant increase in wire delays, Non-Uniform Cache Architecture (NUCA) has been introduced as an effective memory model for dealing with growing memory latencies. This architecture divides a large memory ...
