Exploració per autor "González Colás, Antonio María"
Ara es mostren els items 72-91 de 237
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E-BATCH: Energy-efficient and high-throughput RNN batching
(2022-03)
Article
Accés obertRecurrent Neural Network (RNN) inference exhibits low hardware utilization due to the strict data dependencies across time-steps. Batching multiple requests can increase throughput. However, RNN batching requires a large ... -
E-PUR: an energy-efficient processing unit for recurrent neural networks
(2018)
Text en actes de congrés
Accés restringit per política de l'editorialRecurrent Neural Networks (RNNs) are a key technology for emerging applications such as automatic speech recognition, machine translation or image description. Long Short Term Memory (LSTM) networks are the most successful ... -
Early register release for out-of-order processors with register windows
(Institute of Electrical and Electronics Engineers (IEEE), 2007)
Text en actes de congrés
Accés obertRegister windows is an architectural technique that reduces memory operations required to save and restore registers across procedure calls. Its effectiveness depends on the size of the register file. Such register ... -
Early visibility resolution for removing ineffectual computations in the graphics pipeline
(Institute of Electrical and Electronics Engineers (IEEE), 2019)
Text en actes de congrés
Accés restringit per política de l'editorialGPUs' main workload is real-time image rendering. These applications take a description of a (animated) scene and produce the corresponding image(s). An image is rendered by computing the colors of all its pixels. It is ... -
Effective instruction scheduling techniques for an interleaved cache clustered VLIW processor
(Institute of Electrical and Electronics Engineers (IEEE), 2002)
Text en actes de congrés
Accés obertClustering is a common technique to overcome the wire delay problem incurred by the evolution of technology. Fully-distributed architectures, where the register file, the functional units and the data cache are partitioned, ... -
Effectiveness of hybrid recovery techniques on parametric failures
(Institute of Electrical and Electronics Engineers (IEEE), 2013)
Text en actes de congrés
Accés restringit per política de l'editorialModern day microprocessors effectively utilise supply voltage scaling for tremendous power reduction. The minimum voltage beyond which a processor cannot operate reliably is defined as V ddmin. On-chip memories like caches ... -
Efficient interconnects for clustered microarchitectures
(Institute of Electrical and Electronics Engineers (IEEE), 2002)
Text en actes de congrés
Accés obertClustering is an effective microarchitectural technique for reducing the impact of wire delays, the complexity, and the power requirements of microprocessors. In this work, we investigate the design of on-chip interconnection ... -
Efficient resources assignment schemes for clustered multithreaded processors
(Institute of Electrical and Electronics Engineers (IEEE), 2008)
Text en actes de congrés
Accés obertNew feature sizes provide larger number of transistors per chip that architects could use in order to further exploit instruction level parallelism. However, these technologies bring also new challenges that complicate ... -
Empowering a helper cluster through data-width aware instruction selection policies
(IEEE Computer Society, 2006)
Text en actes de congrés
Accés obertNarrow values that can be represented by less number of bits than the full machine width occur very frequently in programs. On the other hand, clustering mechanisms enable cost- and performance-effective scaling of processor ... -
Energy effective issue logic
(Institute of Electrical and Electronics Engineers (IEEE), 2001)
Text en actes de congrés
Accés obertThe issue logic of a dynamically-scheduled superscalar processor is a complex mechanism devoted to start the execution of multiple instructions every cycle. Due to its complexity, it is responsible for a significant ... -
Energy-efficient stream compaction through filtering and coalescing accesses in GPGPU memory partitions
(Institute of Electrical and Electronics Engineers (IEEE), 2022-07-01)
Article
Accés obertGraph-based applications are essential in emerging domains such as data analytics or machine learning. Data gathering in a knowledge-based society requires great data processing efficiency. High-throughput GPGPU architectures ... -
Executing algorithms with hypercube topology on torus multicomputers
(1995-08)
Article
Accés obertMany parallel algorithms use hypercubes as the communication topology among their processes. When such algorithms are executed on hypercube multicomputers the communication cost is kept minimum since processes can be ... -
Exploiting kernel compression on BNNs
(Institute of Electrical and Electronics Engineers (IEEE), 2023)
Text en actes de congrés
Accés obertBinary Neural Networks (BNNs) are showing tremen-dous success on realistic image classification tasks. Notably, their accuracy is similar to the state-of-the-art accuracy obtained by full-precision models tailored to edge ... -
Exploiting narrow values for soft error tolerance
(2006-07)
Article
Accés obertSoft errors are an important challenge in contemporary microprocessors. Particle hits on the components of a processor are expected to create an increasing number of transient errors with each new microprocessor generation. ... -
Exploiting path parallelism in logic programming
(Institute of Electrical and Electronics Engineers (IEEE), 1995)
Text en actes de congrés
Accés obertThis paper presents a novel parallel implementation of Prolog. The system is based on Multipath, a novel execution model for Prolog that implements a partial breadth-first search of the SLD-tree. The paper focusses on the ... -
Exploiting pseudo-schedules to guide data dependence graph partitioning
(Institute of Electrical and Electronics Engineers (IEEE), 2002)
Text en actes de congrés
Accés obertThis paper presents a new modulo scheduling algorithm for clustered microarchitectures. The main feature of the proposed scheme is that the assignment of instructions to clusters is done by means of graph partitioning ... -
Fast and accurate SER estimation for large combinational blocks in early stages of the design
(Institute of Electrical and Electronics Engineers (IEEE), 2021-07-01)
Article
Accés obertSoft Error Rate (SER) estimation is an important challenge for integrated circuits because of the increased vulnerability brought by technology scaling. This paper presents a methodology to estimate in early stages of the ... -
Fast time-to-market with via-configurable transistor array regular fabric: A delay-locked loop design case study
(IEEE Computer Society Publications, 2011)
Comunicació de congrés
Accés restringit per política de l'editorialTime-to-market is a critical issue for nowadays integrated circuits manufacturers. In this paper the Via-Configurable Transistor Array regular layout fabric (VCTA), which aims to minimize the time-to-market and its associated ... -
Fast, accurate and flexible data locality analysis
(Institute of Electrical and Electronics Engineers (IEEE), 1998)
Text en actes de congrés
Accés obertThis paper presents a tool based on a new approach for analyzing the locality exhibited by data memory references. The tool is very fast because it is based on a static locality analysis enhanced with very simple profiling ... -
FASTM: a log-based hardware transactional memory with fast abort recovery
(IEEE Computer Society, 2009)
Text en actes de congrés
Accés obertVersion management, one of the key design dimensions of Hardware Transactional Memory (HTM) systems, defines where and how transactional modifications are stored. Current HTM systems use either eager or lazy version ...
