Exploració per autor "González Colás, Antonio María"
Ara es mostren els items 37-56 de 237
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Boosting LSTM performance through dynamic precision selection
(Institute of Electrical and Electronics Engineers (IEEE), 2020)
Text en actes de congrés
Accés obertThe use of low numerical precision is a fundamental optimization included in modern accelerators for Deep Neural Networks (DNNs). The number of bits of the numerical representation is set to the minimum precision that is ... -
Boosting point cloud search with a vector unit
(2023)
Report de recerca
Accés obertModern robots collect and process point clouds to perform accurate registration and segmentation. The most time-consuming kernel within point cloud processing -namely neighbor search- relies on appropriate data structures, ... -
Boosting single-thread performance in multi-core systems through fine-grain multi-threading
(ACM Press. Association for Computing Machinery, 2009-06)
Text en actes de congrés
Accés restringit per política de l'editorialIndustry has shifted towards multi-core designs as we have hit the memory and power walls. However, single thread performance remains of paramount importance since some applications have limited thread-level parallelism ... -
Boustrophedonic frames: Quasi-optimal L2 caching for textures in GPUs
(Institute of Electrical and Electronics Engineers (IEEE), 2023)
Text en actes de congrés
Accés obertLiterature is plentiful in works exploiting cache locality for GPUs. A majority of them explore replacement or bypassing policies. In this paper, however, we surpass this exploration by fabricating a formal proof for a ... -
CGPA: Coarse-Grained Pruning of Activations for Energy-Efficient RNN Inference
(2019-09-01)
Article
Accés obertRecurrent neural networks (RNNs) perform element-wise multiplications across the activations of gates. We show that a significant percentage of activations are saturated and propose coarse-grained pruning of activations ... -
Characterizing self-driving tasks in general-purpose architectures
(European Network of Excellence on High Performance and Embedded Architecture and Compilation (HiPEAC), 2021-09-15)
Capítol de llibre
Accés obertAutonomous Vehicles (AVs) have the potential to radically change the automotive industry. How- ever, computing solutions for AVs have to meet severe performance constraints to guarantee a safe driving experience. Current ... -
Chrysso: an integrated power manager for constrained many-core processors
(Association for Computing Machinery (ACM), 2015)
Text en actes de congrés
Accés obertModern microprocessors are increasingly power-constrained as a result of slowed supply voltage scaling (end of Dennard scaling) in conjunction with the transistor density scaling (Moore's Law). Existing many-core power ... -
Circuit propagation delay estimation through multivariate regression-based modeling under spatio-temporal variability
(Institute of Electrical and Electronics Engineers (IEEE), 2010)
Text en actes de congrés
Accés restringit per política de l'editorialWith every process generation, the problem of variability in physical parameters and environmental conditions poses a great challenge to the design of fast and reliable circuits. Propagation delays which decide circuit ... -
Compiler analysis for trace-level speculative multithreaded architectures
(Institute of Electrical and Electronics Engineers (IEEE), 2005)
Text en actes de congrés
Accés obertTrace-level speculative multithreaded processors exploit trace-level speculation by means of two threads working cooperatively. One thread, called the speculative thread, executes instructions ahead of the other by speculating ... -
Compiler directed early register release
(Institute of Electrical and Electronics Engineers (IEEE), 2005)
Text en actes de congrés
Accés obertThis paper presents a novel compiler directed technique to reduce the register pressure and power of the register file by releasing registers early. The compiler identifies registers that mil only be read once and renames ... -
Computation reuse in DNNs by exploiting input similarity
(Institute of Electrical and Electronics Engineers (IEEE), 2018)
Text en actes de congrés
Accés restringit per política de l'editorialIn recent years, Deep Neural Networks (DNNs) have achieved tremendous success for diverse problems such as classification and decision making. Efficient support for DNNs on CPUs, GPUs and accelerators has become a prolific ... -
Control speculation for energy-efficient next-generation superscalar processors
(2006-03)
Article
Accés obertConventional front-end designs attempt to maximize the number of "in-flight" instructions in the pipeline. However, branch mispredictions cause the processor to fetch useless instructions that are eventually squashed, ... -
Control speculation in multithreaded processors through dynamic loop detection
(Institute of Electrical and Electronics Engineers (IEEE), 1998)
Text en actes de congrés
Accés obertThis paper presents a mechanism to dynamically detect the loops that are executed in a program. This technique detects the beginning and the termination of the iterations and executions of the loops without compiler/user ... -
Control-flow independence reuse via dynamic vectorization
(Institute of Electrical and Electronics Engineers (IEEE), 2005)
Text en actes de congrés
Accés obertCurrent processors exploit out-of-order execution and branch prediction to improve instruction level parallelism. When a branch prediction is wrong, processors flush the pipeline and squash all the speculative work. However, ... -
Control-flow speculation through value prediction
(2001-12)
Article
Accés restringit per política de l'editorialIn this paper, we introduce a new branch predictor that predicts the outcome of branches by predicting the value of their inputs and performing an early computation of their results according to the predicted values. The ... -
Control-flow speculation through value prediction for superscalar processors
(Institute of Electrical and Electronics Engineers (IEEE), 1999)
Text en actes de congrés
Accés obertIn this paper, we introduce a new branch predictor that predicts the outcomes of branches by predicting the value of their inputs and performing an early computation of their results according to the predicted values. The ... -
CREW: Computation reuse and efficient weight storage for hardware-accelerated MLPs and RNNs
(2022-08-01)
Article
Accés obertDeep Neural Networks (DNNs) have achieved tremendous success for cognitive applications. The core operation in a DNN is the dot product between quantized inputs and weights. Prior works exploit the weight/input repetition ... -
Cross-layer system reliability assessment framework for hardware faults
(Institute of Electrical and Electronics Engineers (IEEE), 2016)
Text en actes de congrés
Accés obertSystem reliability estimation during early design phases facilitates informed decisions for the integration of effective protection mechanisms against different classes of hardware faults. When not all system abstraction ... -
Data speculative multithreaded architecture
(Institute of Electrical and Electronics Engineers (IEEE), 1998)
Text en actes de congrés
Accés obertWe present a novel processor microarchitecture that relieves three of the most important bottlenecks of superscalar processors: the serialization imposed by true dependences, the relatively small window size and the ... -
DDGacc: boosting dynamic DDG-based binary optimizations through specialized hardware support
(2012)
Text en actes de congrés
Accés restringit per acord de confidencialitatDynamic Binary Translators (DBT) and Dynamic Binary Opti- mization (DBO) by software are used widely for several reasons including performance, design simplification and virtualization. However, the software layer in ...
