Ara es mostren els items 43-53 de 53

    • Self-adaptive hardware architecture with parallel processing capabilities and dynamic reconfiguration 

      Soto Vargas, Javier; Moreno Aróstegui, Juan Manuel; Madrenas Boadas, Jordi; Cabestany Moncusí, Joan (Association for Computing Machinery (ACM), 2017)
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      This paper describes a new self-adaptive hardware architecture with fault tolerance capabilities and a development system that allows the creation of applications. This bioinspired architecture is based on an array of ...
    • Self-controlled 4-transistor low-power min-max current selector 

      Madrenas Boadas, Jordi; Fernández Martínez, Daniel; Cosp Vilella, Jordi; Martínez Alvarado, Luis Arturo; Alarcón Cot, Eduardo José; Vidal López, Eva María; Villar Piqué, Gerard (2009-10)
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      Four cross-coupled MOS transistors operating as switches implement a very compact, fast, low-power and precise minimum and maximum current selector. Local positive feedback allows the circuit to work without the need of ...
    • Sense/Drive Architecture for CMOS-MEMS Accelerometers with Relaxation Oscillator and TDC 

      Michalik, Piotr Jozef; Madrenas Boadas, Jordi; Fernández Martínez, Daniel (IEEE Computational Intelligence Society, 2012)
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    • SIXE: An X-ray experiment for the MINISAT platform 

      Bravo Guil, Eduardo; García-Berro Montilla, Enrique; Gutiérrez Cabello, Jordi; José Pont, Jordi; García Senz, Domingo; Cabestany Moncusí, Joan; Madrenas Boadas, Jordi (2001-01)
      Article
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      SIXE (Spanish Italian X-ray Experiment) is an X-ray payload with geometric area of ~3200 cm2 , formed by four identical gas-filled Multiwire Proportional Counters devoted for a long term spectroscopy of selected X-ray ...
    • SNAVA—A real-time multi-FPGA multi-model spiking neural network simulation architecture 

      Sripad T A, Athul; Sánchez Rivera, Giovanny; Zapata Rodríguez, Mireya; Pirrone, Vito; Dorta Pérez, Silvestre Taho; Cambria, Salvatore; Marti, Albert; Krishnamourthy, Karthikeyan; Madrenas Boadas, Jordi (2018-01-01)
      Article
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      Spiking Neural Networks (SNN) for Versatile Applications (SNAVA) simulation platform is a scalable and programmable parallel architecture that supports real-time, large-scale, multi-model SNN computation. This parallel ...
    • Spike-based analog-digital neuromorphic information processing system for sensor applications 

      Sánchez Rivera, Giovanny; Koickal, Thomas Jacob; Sripad T A, Athul; Gouveia, Luiz Carlos; Hamilton, Alister; Madrenas Boadas, Jordi (Institute of Electrical and Electronics Engineers (IEEE), 2013)
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      A spiking-neuron-based system that combines analog and digital multi-processor implementations for the bio-inspired processing of sensors is reported. This combination allows creating a powerful bio-inspired multiple-input ...
    • SpiNDeK: An integrated design tool for the multiprocessor emulation of complex bioinspired spiking neural networks 

      Hauptvogel, Michael; Madrenas Boadas, Jordi; Moreno Aróstegui, Juan Manuel (IEEE Computer Society Publications, 2009)
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      SpiNDeK (Spiking Neural Network Design Kit) is an integrated design tool intended to support the development of emulation of complex bioinspired neural networks. In this work, the most relevant aspects of the tool are ...
    • Synchronizable compact CMOS oscillator 

      Villar Piqué, Gerard; Alarcón Cot, Eduardo José; Vidal López, Eva María; Cosp Vilella, Jordi; Madrenas Boadas, Jordi (2005-01)
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      This letter describes the design and implementation of a synchronizable compact CMOS oscillator. By using a fully differential topology, a reduction in area occupancy together with an improved robustness in front of on-chip ...
    • Synchronization of nonlinear electronic oscillators for neural computation 

      Cosp Vilella, Jordi; Madrenas Boadas, Jordi; Alarcón Cot, Eduardo José; Vidal López, Eva María; Villar Piqué, Gerard (2004-09)
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      This paper deals with coupled oscillators as the building blocks of a bioinspired computing paradigm and their implementation. In order to accomplish the low-power and fast-processing requirements of autonomous applications, ...
    • Synchronous digital implementation of the AER communication scheme for emulating large-scale spiking neural networks models 

      Moreno Aróstegui, Juan Manuel; Madrenas Boadas, Jordi; Kotynia, L. (IEEE Computer Society Publications, 2009-08)
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      In this paper we shall present a fully synchronous digital implementation of the Address Event Representation (AER) communication scheme that has been used in the PERPLEXUS chip in order to permit the emulation ...
    • Translinear signal processing circuits in standard CMOS FPAA 

      Martínez Alvarado, Luis Arturo; Madrenas Boadas, Jordi; Fernández Martínez, Daniel (IEEE Press. Institute of Electrical and Electronics Engineers, 2009-12)
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      In this paper, the implementation of signal processing circuits on a novel translinear Field-Programmable Analog Array (FPAA) testchip is reported. The FPAA testchip is based on a 0.35-micron, fully CMOS translinear ...