Exploració per autor "Madrenas Boadas, Jordi"
Ara es mostren els items 37-53 de 53
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Optimization of parameters for CMOS MEMS resonant pressure sensors
(Institute of Electrical and Electronics Engineers (IEEE), 2015)
Text en actes de congrés
Accés restringit per política de l'editorialMicro machined resonant pressure sensors have rapidly grown into a major type of MEMS products over the past two decades. This paper presents the mathematical modelling of squeeze film damping in a MEMS resonant pressure ... -
Performance evaluation and scaling of a multiprocessor architecture emulating complex SNN algorithms
(Springer Verlag, 2010-09)
Article
Accés restringit per política de l'editorialThe performance analysis of an efficient multiprocessor architecture that allows accelerating the emulation of large-scale Spiking Neural Networks (SNNs) is reported. After describing the architecture and the complex SNN ... -
Pulsed digital oscillators for electrostatic MEMS
(2012)
Article
Accés restringit per política de l'editorialThis paper introduces a new actuation scheme for implementing Pulsed Digital Oscillators (PDOs) for electrostatic MEMS resonators. In this scheme, the capacitance of the device is biased with a voltage and it is periodically ... -
Quasi-digital conversion for resistive devices: application in GMR-based IC current sensors
(Institute of Electrical and Electronics Engineers (IEEE), 2013)
Text en actes de congrés
Accés restringit per política de l'editorialResistive devices, including sensors, are used in a huge range of applications within different scenarios. When a complete system is considered, a quasi-digital output is often recommendable. If the conversion is operated ... -
Quasi-digital front-ends for current measurement in integrated circuits with giant magnetoresistance technology
(2014-07-01)
Article
Accés restringit per política de l'editorialIn this study, the authors report on two different electronic interfaces for low-power integrated circuits electric current monitoring through current-to-frequency (I-f) conversion schemes. This proposal displays the ... -
Result-consistent counter sampling scheme for coarse-fine TDCs
(Institution of Electrical Engineers, 2012-09-13)
Article
Accés restringit per política de l'editorial -
Self-adaptive hardware architecture with parallel processing capabilities and dynamic reconfiguration
(Association for Computing Machinery (ACM), 2017)
Text en actes de congrés
Accés restringit per política de l'editorialThis paper describes a new self-adaptive hardware architecture with fault tolerance capabilities and a development system that allows the creation of applications. This bioinspired architecture is based on an array of ... -
Self-controlled 4-transistor low-power min-max current selector
(2009-10)
Article
Accés restringit per política de l'editorialFour cross-coupled MOS transistors operating as switches implement a very compact, fast, low-power and precise minimum and maximum current selector. Local positive feedback allows the circuit to work without the need of ... -
Sense/Drive Architecture for CMOS-MEMS Accelerometers with Relaxation Oscillator and TDC
(IEEE Computational Intelligence Society, 2012)
Text en actes de congrés
Accés obert -
SIXE: An X-ray experiment for the MINISAT platform
(2001-01)
Article
Accés restringit per política de l'editorialSIXE (Spanish Italian X-ray Experiment) is an X-ray payload with geometric area of ~3200 cm2 , formed by four identical gas-filled Multiwire Proportional Counters devoted for a long term spectroscopy of selected X-ray ... -
SNAVA—A real-time multi-FPGA multi-model spiking neural network simulation architecture
(2018-01-01)
Article
Accés obertSpiking Neural Networks (SNN) for Versatile Applications (SNAVA) simulation platform is a scalable and programmable parallel architecture that supports real-time, large-scale, multi-model SNN computation. This parallel ... -
Spike-based analog-digital neuromorphic information processing system for sensor applications
(Institute of Electrical and Electronics Engineers (IEEE), 2013)
Text en actes de congrés
Accés restringit per política de l'editorialA spiking-neuron-based system that combines analog and digital multi-processor implementations for the bio-inspired processing of sensors is reported. This combination allows creating a powerful bio-inspired multiple-input ... -
SpiNDeK: An integrated design tool for the multiprocessor emulation of complex bioinspired spiking neural networks
(IEEE Computer Society Publications, 2009)
Text en actes de congrés
Accés restringit per política de l'editorialSpiNDeK (Spiking Neural Network Design Kit) is an integrated design tool intended to support the development of emulation of complex bioinspired neural networks. In this work, the most relevant aspects of the tool are ... -
Synchronizable compact CMOS oscillator
(2005-01)
Article
Accés restringit per política de l'editorialThis letter describes the design and implementation of a synchronizable compact CMOS oscillator. By using a fully differential topology, a reduction in area occupancy together with an improved robustness in front of on-chip ... -
Synchronization of nonlinear electronic oscillators for neural computation
(2004-09)
Article
Accés restringit per política de l'editorialThis paper deals with coupled oscillators as the building blocks of a bioinspired computing paradigm and their implementation. In order to accomplish the low-power and fast-processing requirements of autonomous applications, ... -
Synchronous digital implementation of the AER communication scheme for emulating large-scale spiking neural networks models
(IEEE Computer Society Publications, 2009-08)
Text en actes de congrés
Accés obertIn this paper we shall present a fully synchronous digital implementation of the Address Event Representation (AER) communication scheme that has been used in the PERPLEXUS chip in order to permit the emulation ... -
Translinear signal processing circuits in standard CMOS FPAA
(IEEE Press. Institute of Electrical and Electronics Engineers, 2009-12)
Text en actes de congrés
Accés obertIn this paper, the implementation of signal processing circuits on a novel translinear Field-Programmable Analog Array (FPAA) testchip is reported. The FPAA testchip is based on a 0.35-micron, fully CMOS translinear ...
