Exploració per autor "Ayguadé Parra, Eduard"
Ara es mostren els items 235-254 de 326
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QuakeTM: Parallelizing a complex serial application using transactional memory
Gajinov, Vladimir; Zyulkyarov, Ferad; Unsal, Osman Sabri; Cristal Kestelman, Adrián; Ayguadé Parra, Eduard; Harris, Tim; Valero Cortés, Mateo (2008-11)
Report de recerca
Accés obert'Is transactional memory useful?' is the question that cannot be answered until we provide substantial applications that can evaluate its capabilities. While existing TM applications can partially answer the above question, ... -
Quantifying the benefits of SPECint distant parallelism in simultaneous multithreading architectures
Ortega Fernández, Daniel; Martel Pérez, Iván; Krishnan, Venkata; Ayguadé Parra, Eduard; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 1999)
Text en actes de congrés
Accés obertWe exploit the existence of distant parallelism that future compilers could detect and characterise its performance under simultaneous multithreading architectures. By distant parallelism we mean parallelism that cannot ... -
Quantitative analysis of vector code
Espasa Sans, Roger; Valero Cortés, Mateo; Padua, David; Jiménez Castells, Marta; Ayguadé Parra, Eduard (Institute of Electrical and Electronics Engineers (IEEE), 1995)
Text en actes de congrés
Accés obertIn this paper we present the results of a detailed simulation study of the execution of vector programs on a single processor of a Convex C3480 machine, using a subset of the Perfect Club benchmarks. We are interested in ... -
Quantitative evaluation of register pressure on software pipeline loops
Llosa Espuny, José Francisco; Ayguadé Parra, Eduard; Valero Cortés, Mateo (1998-02)
Article
Accés restringit per política de l'editorialSoftware Pipelining is a loop scheduling technique that extracts loop parallelism by overlapping the execution of several consecutive iterations. One of the drawbacks of software pipelining is its high register requirements, ... -
Random forest as a tumour genetic marker extractor
Pérez Arnal, Raquel Leandra; Garcia Gasulla, Dario; Torrents Rodas, David; Pares, Ferran; Cortés García, Claudio Ulises; Labarta Mancho, Jesús José; Ayguadé Parra, Eduard (IOS Press, 2019)
Text en actes de congrés
Accés obertFinding tumour genetic markers is essential to biomedicine due to their relevance for cancer detection and therapy development. In this paper, we explore a recently released dataset of chromosome rearrangements in 2,586 ... -
Reconfigurable memory controller with programmable pattern support
Hussain, Tassadaq; Pericas, Miquel; Ayguadé Parra, Eduard (2011)
Text en actes de congrés
Accés restringit per política de l'editorialHeterogeneous architectures are increasingly popular due to their flexibility and high performance per watt capability. A kind of heterogeneous architecture, reconfigurable systems-on-chip, offer high performance per watt ... -
Reducing cache coherence traffic with hierarchical directory cache and NUMA-aware runtime scheduling
Caheny, Paul; Casas, Marc; Moretó Planas, Miquel; Gloaguen, Hervé; Saintes, Maxime; Ayguadé Parra, Eduard; Labarta Mancho, Jesús José; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2016)
Text en actes de congrés
Accés obertCache Coherent NUMA (ccNUMA) architectures are a widespread paradigm due to the benefits they provide for scaling core count and memory capacity. Also, the flat memory address space they offer considerably improves ... -
Reducing data movement on large shared memory systems by exploiting computation dependencies
Barrera, I.S.; Ayguadé Parra, Eduard; Valero Cortés, Mateo; Moretó Planas, Miquel; Labarta Mancho, Jesús José; Casas, Marc (Association for Computing Machinery (ACM), 2018)
Text en actes de congrés
Accés obertShared memory systems are becoming increasingly complex as they typically integrate several storage devices. That brings different access latencies or bandwidth rates depending on the proximity between the cores where ... -
Register constrained modulo scheduling
Zalamea León, Francisco Javier; Llosa Espuny, José Francisco; Ayguadé Parra, Eduard; Valero Cortés, Mateo (2004-05)
Article
Accés restringit per política de l'editorialSoftware pipelining is an instruction scheduling technique that exploits the instruction level parallelism (ILP) available in loops by overlapping operations from various successive loop iterations. The main drawback of ... -
Running OpenMP application efficiently on an everything-shared SDSM
Costa Prats, Juan José; Cortés, Toni; Martorell Bofill, Xavier; Ayguadé Parra, Eduard; Labarta Mancho, Jesús José (2006-05)
Article
Accés restringit per política de l'editorialTraditional software distributed shared memory (SDSM) systems modify the semantics of a real hardware shared memory system by relaxing the coherence semantic and by limiting the memory regions that are actually shared. ... -
Running OpenMp applications efficiently on an everything-shared SDSM
Costa Prats, Juan José; Cortés, Toni; Martorell Bofill, Xavier; Ayguadé Parra, Eduard; Labarta Mancho, Jesús José (Institute of Electrical and Electronics Engineers (IEEE), 2004)
Comunicació de congrés
Accés obertTraditional software distributed shared memory (SDSM) systems modify the semantics of a real hardware shared memory system by relaxing the coherence semantic and by limiting the memory regions that are actually shared. ... -
Runtime address space computation for SDSM systems
Balart Tarzan, Jairo; González Tallada, Marc; Martorell Bofill, Xavier; Ayguadé Parra, Eduard; Labarta Mancho, Jesús José (2007)
Article
Accés obertThis paper explores the benefits and limitations of using a inspector/executor approach for Software Distributed Shared Memory (SDSM) systems. The role of the inspector is to obtain a description of the address space ... -
Runtime vs. manual data distribution for architecture-agnostic shared-memory programming models
Nikolopoulos, Dimitrios; Ayguadé Parra, Eduard; Polychronopoulos, C D (2002-08)
Article
Accés restringit per política de l'editorialThis paper compares data distribution methodologies for scaling the performance of OpenMP on NUMA architectures. We investigate the performance of automatic page placement algorithms implemented in the operating system, ... -
Runtime-aware architectures
Casas, Marc; Moretó Planas, Miquel; Álvarez Martí, Lluc; Castillo Villar, Emilio; Chasapis, Dimitrios; Hayes, Timothy; Jaulmes, Luc; Palomar Pérez, Óscar; Unsal, Osman Sabri; Cristal Kestelman, Adrián; Ayguadé Parra, Eduard; Labarta Mancho, Jesús José; Valero Cortés, Mateo (Springer, 2015)
Text en actes de congrés
Accés obertIn the last few years, the traditional ways to keep the increase of hardware performance to the rate predicted by the Moore’s Law have vanished. When uni-cores were the norm, hardware design was decoupled from the software ... -
Runtime-aware architectures: a first approach
Valero Cortés, Mateo; Moretó Planas, Miquel; Casas, Marc; Ayguadé Parra, Eduard; Labarta Mancho, Jesús José (2014)
Article
Accés obertIn the last few years, the traditional ways to keep the increase of hardware performance at the rate predicted by Moore's Law have vanished. When uni-cores were the norm, hardware design was decoupled from the software ... -
Runtime-guided management of scratchpad memories in multicore architectures
Álvarez Martí, Lluc; Moretó Planas, Miquel; Casas, Marc; Castillo Villar, Emilio; Martorell Bofill, Xavier; Labarta Mancho, Jesús José; Ayguadé Parra, Eduard; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2015)
Text en actes de congrés
Accés obertThe increasing number of cores and the anticipated level of heterogeneity in upcoming multicore architectures cause important problems in traditional cache hierarchies. A good way to alleviate these problems is to add ... -
Runtime-guided management of stacked DRAM memories in task parallel programs
Álvarez Martí, Lluc; Casas, Marc; Labarta Mancho, Jesús José; Ayguadé Parra, Eduard; Valero Cortés, Mateo; Moretó Planas, Miquel (Association for Computing Machinery (ACM), 2018)
Text en actes de congrés
Accés obertStacked DRAM memories have become a reality in High-Performance Computing (HPC) architectures. These memories provide much higher bandwidth while consuming less power than traditional off-chip memories, but their limited ... -
Runtime-guided mitigation of manufacturing variability in power-constrained multi-socket NUMA nodes
Chasapis, Dimitrios; Casas, Marc; Moretó Planas, Miquel; Schulz, Martin; Ayguadé Parra, Eduard; Labarta Mancho, Jesús José; Valero Cortés, Mateo (Association for Computing Machinery (ACM), 2016)
Comunicació de congrés
Accés obert -
Saiph: towards a DSL for high-performance computational fluid dynamics
Macià, Sandra; Mateo, Sergi; Martínez-Ferrer, Pedro J.; Beltran Querol, Vicenç; Mira Martínez, Daniel; Ayguadé Parra, Eduard (Association for Computing Machinery (ACM), 2018)
Text en actes de congrés
Accés restringit per política de l'editorialNowadays high-performance computing is taking an increasingly central role in scientific research while computer architectures are becoming more heterogeneous and complex with different parallel programming models and ... -
Sampled simulation of task-based programs
Grass, Thomas; Carlson, Trevor E.; Rico Carro, Alejandro; Ceballos, Germán; Ayguadé Parra, Eduard; Casas, Marc; Moretó Planas, Miquel (Institute of Electrical and Electronics Engineers (IEEE), 2019-02-01)
Article
Accés obertSampled simulation is a mature technique for reducing simulation time of single-threaded programs. Nevertheless, current sampling techniques do not take advantage of other execution models, like task-based execution, to ...