Exploració per autor "Ayguadé Parra, Eduard"
Ara es mostren els items 160-179 de 326
-
Java instrumentation suite: accurate analysis of Java threaded applications
(2000)
Text en actes de congrés
Accés obertThe rapid maturing process of the Java technology is encouraging users the development of portable applications using the Java language. As an important part of the definition of the Java language, the use of threads is ... -
Large-memory nodes for energy efficient high-performance computing
(Association for Computing Machinery (ACM), 2016)
Text en actes de congrés
Accés obertEnergy consumption is by far the most important contributor to HPC cluster operational costs, and it accounts for a significant share of the total cost of ownership. Advanced energy-saving techniques in HPC components have ... -
Leveraging OmpSs to exploit hardware accelerators
(Institute of Electrical and Electronics Engineers (IEEE), 2014)
Text en actes de congrés
Accés restringit per política de l'editorialCUDA and OpenCL are the most widely used programming models to exploit hardware accelerators. Both programming models provide a C-based programming language to write accelerator kernels and a host API used to glue the host ... -
Lifetime-sensitive modulo scheduling in a production environment
(2001-03)
Article
Accés obertThis paper presents a novel software pipelining approach, which is called Swing Modulo Scheduling (SMS). It generates schedules that are near optimal in terms of initiation interval, register requirements, and stage count. ... -
Lightning talks of EduHPC 2022
(Institute of Electrical and Electronics Engineers (IEEE), 2022)
Text en actes de congrés
Accés obertThe lightning talks at EduHPC provide an opportunity to share early results and insights on parallel and distributed computing (PDC) education and training efforts. The four lightning talks at EduHPC 2022 cover a range of ... -
Loop level speculation in a task based programming model
(2013)
Text en actes de congrés
Accés obertUncountable loops (such as while loops in C) and if-conditions are some of the most common constructs in programming. While-loops are widely used to determine the convergence in linear algebra algorithms or goal finding ... -
Loop parallelization: revisiting framework of unimodular transformations
(Institute of Electrical and Electronics Engineers (IEEE), 1996)
Text en actes de congrés
Accés obertThe paper extends the framework of linear loop transformations adding a new nonlinear step at the transformation process. The current framework of linear loop transformation cannot identify a significant fraction of ... -
Low-latency multi-threaded ensemble learning for dynamic big data streams
(Institute of Electrical and Electronics Engineers (IEEE), 2018)
Text en actes de congrés
Accés obertReal–time mining of evolving data streams involves new challenges when targeting today’s application domains such as the Internet of the Things: increasing volume, velocity and volatility requires data to be processed ... -
MACC: Mercurium ACCelerator Model
(Barcelona Supercomputing Center, 2015-05-05)
Text en actes de congrés
Accés obertGPU Offloading is emergent programming model. OpenMP includes in its latest 4.0 specification the accelerator model. In this paper we present a newly implementation of this specification while generationg "native" GPU ... -
Main memory in HPC: do we need more or could we live with less?
(Barcelona Supercomputing Center, 2017-05-04)
Text en actes de congrés
Accés obertThis study analyzes the memory capacity requirements of important HPC benchmarks and applications. We find that the High Performance Conjugate Gradients benchmark could be an important success story for 3D-stacked memories ... -
Main memory in HPC: do we need more, or could we live with less?
(2017-03)
Article
Accés obertAn important aspect of High-Performance Computing (HPC) system design is the choice of main memory capacity. This choice becomes increasingly important now that 3D-stacked memories are entering the market. Compared with ... -
Main memory latency simulation: the missing link
(Association for Computing Machinery (ACM), 2018)
Text en actes de congrés
Accés obertThe community accepted the need for a detailed simulation of main memory. Currently, the CPU simulators are usually coupled with the cycle-accurate main memory simulators. However, coupling CPU and memory simulators is not ... -
Mainstream vs. emerging HPC: metrics, trade-offs and lessons learned
(Institute of Electrical and Electronics Engineers (IEEE), 2018)
Text en actes de congrés
Accés obertVarious servers with different characteristics and architectures are hitting the market, and their evaluation and comparison in terms of HPC features is complex and multidimensional. In this paper, we share our experience ... -
Managing SLAs of heterogeneous workloads using dynamic application placement
(ACM Press, NY, 2008)
Text en actes de congrés
Accés obertIn this paper we address the problem of managing heterogeneous workloads in a virtualized data center. We consider two different workloads: transactional applications and long-running jobs. We present a technique that ... -
MAPC: memory access pattern based controller
(Institute of Electrical and Electronics Engineers (IEEE), 2014)
Text en actes de congrés
Accés restringit per política de l'editorialTraditionally, system designers have attempted to improve system performance by scheduling the processing cores and by exploring different memory system configurations and there is comparatively less work done scheduling ... -
MAPC: memory access pattern based controller
(Institute of Electrical and Electronics Engineers (IEEE), 2014)
Text en actes de congrés
Accés restringit per política de l'editorialTraditionally, system designers have attempted to improve system performance by scheduling the processing cores and by exploring different memory system configurations and there is comparatively less work done scheduling ... -
Mapping stream programs onto heterogeneous multiprocessor systems
(ACM Press, NY, 2009)
Comunicació de congrés
Accés restringit per política de l'editorialThis paper presents a partitioning and allocation algorithm for an iterative stream compiler, targeting heterogeneous multiprocessors with constrained distributed memory and any communications topology. We introduce a ... -
MASA: a multi-platform architecture for sequence aligners with block pruning
(2016-03-01)
Article
Accés obertBiological sequence alignment is a very popular application in Bioinformatics used routinely worldwide. Many implementations of biological sequence alignment algorithms have been proposed for multicores, GPUs, FPGAs and ... -
Memory controller for vector processor
(Springer, 2018-11)
Article
Accés obertTo manage power and memory wall affects, the HPC industry supports FPGA reconfigurable accelerators and vector processing cores for data-intensive scientific applications. FPGA based vector accelerators are used to increase ... -
MetH: A family of high-resolution and variable-shape image challenges
(2019-11-20)
Report de recerca
Accés obertHigh-resolution and variable-shape images have not yet been properly addressed by the AI community. The approach of down-sampling data often used with convolutional neural networks is sub-optimal for many tasks, and has ...
