Exploració per autor "Navarro, Nacho"
Ara es mostren els items 14-33 de 35
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Data stream classification using random feature functions and novel method combinations
(2017-05-01)
Article
Accés obertBig Data streams are being generated in a faster, bigger, and more commonplace. In this scenario, Hoeffding Trees are an established method for classification. Several extensions exist, including high performing ensemble ... -
Design space explorations for streaming accelerators using streaming architectural simulator
(Institute of Electrical and Electronics Engineers (IEEE), 2013)
Text en actes de congrés
Accés obertIn the recent years streaming accelerators like GPUs have been pop-up as an effective step towards parallel computing. The wish-list for these devices span from having a support for thousands of small cores to a nature ... -
Direct Inter-Process Communication (dIPC): Repurposing the CODOMs architecture to accelerate IPC
(Association for Computing Machinery (ACM), 2017)
Text en actes de congrés
Accés obertIn current architectures, page tables are the fundamental mechanism that allows contemporary OSs to isolate user processes, binding each thread to a specific page table. A thread cannot therefore directly call another ... -
Efficient exception handling support for GPUs
(Association for Computing Machinery (ACM), 2017)
Text en actes de congrés
Accés restringit per política de l'editorialOperating systems have long relied on the exception handling mechanism to implement numerous virtual memory features and optimizations. However, today's GPUs have a limited support for exceptions, which prevents implementation ... -
Enabling preemptive multiprogramming on GPUs
(Institute of Electrical and Electronics Engineers (IEEE), 2014)
Text en actes de congrés
Accés obertGPUs are being increasingly adopted as compute accelerators in many domains, spanning environments from mobile systems to cloud computing. These systems are usually running multiple applications, from one or several users. ... -
Experimental assessment of a high performance back-end PCE for Flexgrid optical network re-optimization
(The Optical Society (OSA), 2014)
Text en actes de congrés
Accés restringit per política de l'editorialA specialized high performance Graphics Processing Unit (GPU)-based back-end Path Computation Element (PCE) to compute re-optimization in Flexgrid networks is presented. Experimental results show 6x speedups compared to ... -
Hardware-software coherence protocol for the coexistence of caches and local memories
(2015-01-01)
Article
Accés obertCache coherence protocols limit the scalability of multicore and manycore architectures and are responsible for an important amount of the power consumed in the chip. A good way to alleviate these problems is to introduce ... -
High-performance reverse time migration on GPU
(2009-11)
Text en actes de congrés
Accés obertPartial Differential Equations (PDE) are the heart of most simulations in many scientific fields, from Fluid Mechanics to Astrophysics. One the most popular mathematical schemes to solve a PDE is Finite Difference (FD). In ... -
iONE: an environment for experimentally assessing in-operation network planning algorithms
(Institute of Electrical and Electronics Engineers (IEEE), 2015)
Text en actes de congrés
Accés restringit per política de l'editorialHuge amount of algorithmic research is being done in the field of optical networks, including Routing and Spectrum Allocation (RSA), elastic operations, spectrum defragmentation, and other re-optimization algorithms. ... -
Kernel-level scheduling for the nano-threads programming model
(Associaton for Computing Machinery (ACM), 1998)
Text en actes de congrés
Accés obertMultiprocessor systems are increasingly becoming the sys- tems of choice for low and high-end servers, running such diverse tasks as number crunching, large-scale simulations, data base engines and world wide web server ... -
NanosCompiler: supporting flexible multilevel parallelism exploitation in OpenMP
(2000-10)
Article
Accés restringit per política de l'editorialThis paper describes the support provided by the NanosCompiler to nested parallelism in OpenMP. The NanosCompiler is a source-to-source parallelizing compiler implemented around a hierarchical internal program representation ... -
On-Chip memories, the OS perspective
(2008-06-04)
Text en actes de congrés
Accés obertThis paper is a work in progress study of the operating system services required to manage on-chip memories. We are evaluating different CMP on-chip memories configurations. Chip-MultiProcessors (CMP) architectures ... -
Optimization of atmospheric transport models on HPC platforms
(Elsevier, 2016-12)
Article
Accés obertThe performance and scalability of atmospheric transport models on high performance computing environments is often far from optimal for multiple reasons including, for example, sequential input and output, synchronous ... -
Optimization of atmospheric transport models on HPC platforms
(2016-12)
Article
Accés obertThe performance and scalability of atmospheric transport models on high performance computing environments is often far from optimal for multiple reasons including, for example, sequential input and output, synchronous ... -
Predictive runtime code scheduling for heterogeneous architectures
(2009)
Text en actes de congrés
Accés obertHeterogeneous architectures are currently widespread. With the advent of easy-to-program general purpose GPUs, virtually every re- cent desktop computer is a heterogeneous system. Combining the CPU and the GPU brings ... -
Simulating next-generation Cyber-physical computing platforms
(2015)
Text en actes de congrés
Accés restringit per política de l'editorialIn specific domains, such as cyber-physical systems, platforms are quickly evolving to include multiple (many-) cores and programmable logic in a single system-on-chip, while includ- ing interfaces to commodity ... -
Software-managed power reduction in Infiniband links
(Institute of Electrical and Electronics Engineers (IEEE), 2014)
Text en actes de congrés
Accés obertThe backbone of a large-scale supercomputer is the interconnection network. As compute nodes become more energy-efficient, the interconnect is accounting for an increasing proportion of the total system energy consumption. ... -
The AXIOM project (Agile, eXtensible, fast I/O Module)
(Institute of Electrical and Electronics Engineers (IEEE), 2015)
Text en actes de congrés
Accés restringit per política de l'editorialThe AXIOM project (Agile, eXtensible, fast I/O Module) aims at researching new software/hardware architectures for the future Cyber-Physical Systems (CPSs). These systems are expected to react in real-time, provide enough ... -
The AXIOM software layers
(2016-11-01)
Article
Accés obertAXIOM project aims at developing a heterogeneous computing board (SMP-FPGA).The Software Layers developed at the AXIOM project are explained.OmpSs provides an easy way to execute heterogeneous codes in multiple cores. ... -
The AXIOM software layers
(Institute of Electrical and Electronics Engineers (IEEE), 2015)
Text en actes de congrés
Accés restringit per política de l'editorialPeople and objects will soon share the same digital network for information exchange in a world named as the age of the cyber-physical systems. The general expectation is that people and systems will interact in real-time. ...
